SAF7118 View Datasheet(PDF) - Philips Electronics

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SAF7118

Multistandard video decoder with adaptive comb filter and component video input

Philips Electronics 

Philips Semiconductors

Multistandard video decoder with adaptive

comb filter and component video input

Product specification

SAF7118

Table 9 Processing trigger and start

XDV1

92H[5]

0

0

0

XDV0

92H[4]

1

0

0

XDH

92H[2]

0

0

0

DESCRIPTION

Internal decoder: The processing triggers at the falling edge of the V123 pulse

[see Figs 28 (50 Hz) and 29 (60 Hz)], and starts earliest with the rising edge of the

decoder HREF at line number:

4/7 (50/60 Hz, 1st field), respectively 3/6 (50/60 Hz, 2nd field) (decoder count)

2/5 (50/60 Hz, 1st field), respectively 2/5 (50/60 Hz, 2nd field) (decoder count)

External ITU 656 stream: The processing starts earliest with SAV at line number 23

(50 Hz system), respectively line 20 (60 Hz system) (according to ITU 656 count)

8.4.1.2 Task handling

The task handler controls the switching between the two

programming register sets. It is controlled by

subaddresses 90H and C0H. A task is enabled via the

global control bits TEA[80H[4]] and TEB[80H[5]].

The handler is then triggered by events, which can be

defined for each register set.

In the event of a programming error the task handling and

the complete scaler can be reset to the initial states by

setting the software reset bit SWRST[88H[5]] to logic 0.

Especially if the programming registers, related acquisition

window and scale are reprogrammed while a task is active,

a software reset must be performed after programming.

Contrary to the disabling/enabling of a task, which is

evaluated at the end of a running task, when SWRST is at

logic 0 it sets the internal state machines directly to their

idle states.

The start condition for the handler is defined by bits

STRC[1:0] 90H[1:0] and means: start immediately, wait for

next V-sync, next FID at logic 0 or next FID at logic 1. The

FID is evaluated, if the vertical and horizontal offsets are

reached.

When RPTSK[90H[2]] is at logic 1 the actual running task

is repeated (under the defined trigger conditions), before

handing control over to the alternate task.

To support field rate reduction, the handler is also enabled

to skip fields (bits FSKP[2:0] 90H[5:3]) before executing

the task. A TOGGLE flag is generated (used for the correct

output field processing), which changes state at the

beginning of a task, every time a task is activated;

examples are given in Section 8.4.1.3.

Remarks:

• To activate a task the start condition must be

fulfilled and the acquisition window offsets must be

reached.

For example, in case of ‘start immediately’, and two

regions are defined for one field, the offset of the lower

region must be greater than (offset + length) of the

upper region, if not, the actual counted H and V position

at the end of the upper task is beyond the programmed

offsets and the processing will ‘wait for next V’.

• Basically the trigger conditions are checked, when a

task is activated. It is important to realize, that they are

not checked while a task is inactive. So you can not

trigger to next logic 0 or logic 1 with overlapping offset

and active video ranges between the tasks (e.g. task A

STRC[2:0] = 2, YO[11:0] = 310 and task B

STRC[2:0] = 3, YO[11:0] = 310 results in output field

rate of 50⁄3 Hz).

• After power-on or software reset (via

SWRST[88H[5]]) task B gets priority over task A.

8.4.1.3 Output field processing

As a reference for the output field processing, two signals

are available for the back-end hardware.

These signals are the input field ID from the scaler source

and a TOGGLE flag, which shows that an active task is

used an odd (1, 3, 5...) or even (2, 4, 6...) number of times.

Using a single or both tasks and reducing the field or frame

rate with the task handling function, the TOGGLE

information can be used to reconstruct an interlaced

scaled picture at a reduced frame rate. The TOGGLE flag

isn’t synchronized to the input field detection, as it is only

dependent on the interpretation of this information by the

external hardware, whether the output of the scaler is

processed correctly; see Section 8.4.3.

2004 Jul 22

49

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