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SAA7115 View Datasheet(PDF) - Philips Electronics

Part NameDescriptionManufacturer
SAA7115 PAL/NTSC/SECAM Video Decoder with Adaptive PAL/NTSC Comb Filter, High Performance Scaler, I2C Sliced Data Readback and SQ Pixel Output Philips
Philips Electronics Philips
SAA7115 Datasheet PDF : 214 Pages
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Philips Semiconductors
CS-PD Hamburg
2.7 Summary SAA7114 versus SAA7115
CVIP2
Datasheet
SAA7115
Date:
Version:
10/23/01
0.67
Table 1 SAA7114 versus SAA7115
ISSUE
SAA7114
SAA7115
Pin compatibility
reference pinning
pin-compatible to SAA7114
Analog Frontend
2 x 9 bit A/D- converters
2 x Low Noise 9 bit A/D- converters
13.5 MHz CCIR sampling
27 MHz CCIR 2x-oversampling
Standard White-Peak Control watching raw data Standard White-Peak Control watching
raw data plus baseband luminance data
Combfilter Decoder
4 lines adaptive comb filter
Improved 4 lines adaptive comb filter
(reduced artifacts)
Manual TV/VCR switching
Automatic TV/VCR detection
Semi-automatic color standard detection
Fully-automatic color standard detection
Regular SECAM 50 Hz
Regular SECAM 50 Hz and SECAM 60
Hz (Vietnam)
Color overflow detection
Automatic color reducer (avoids color
limitation with low burst)
Safe lock for VCR feature modes
Extended safe lock for VCR feature
modes
Fast frame lock (ca. 2 fields)
Ultra-fast frame lock (almost 1 field)
Macrovision
Detection
‘Pseudo Sync.’Macrovision Detection only
Comprehensive Macrovision Detection:
- ‘Pseudo Sync.’ detection and/or
- Split Burst detection (Type 2 / Type 3)
Scaled Video Output
Generation of embedded ITU-656 auxiliary
codes at the I-Port video output
Generation of embedded ITU-656
auxiliary codes at the I-Port video output
with improved synchronization raster for
VCR signals
Clock Generation
Scaling to Square Pixel Data representation
Scaling to Square Pixel Data
representation with extra integrated
clock-PLL (PLL2, CGC2) to generate
physical Square Pixel Clock signal of 29.5
MHz (PAL) or 24.5454 MHz (NTSC).
Field- locked audio clock (constant number of
clock cycles per field)
Frame- locked audio clock (constant
number of clock cycles per frame),
optionally through analog PLL (CGC2)
VBI Data Slicing and
Output
Versatile VBI- data slicer
Versatile VBI- data slicer, incl. CGMS
(Line 20 NTSC) and GemStar 2x (EPG)
Output of sliced data embedded into I-Port
output stream
Output of sliced data embedded into
I-Port output stream and optionally
per I2C register readback for
CC, CGMS, Gemstar1x and Gemstar2x,
Confidential - NDA required
Filename: SAA7115_Datasheet.fm
page 9
Last edited by H. Lambers
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