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SAA7115 View Datasheet(PDF) - Philips Electronics

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SAA7115 Datasheet PDF : 214 Pages
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Philips Semiconductors
CS-PD Hamburg
– WSS525 (CGMS)
– WSS625 (CGMS)
– GEMSTAR 1x
– GEMSTAR 2x
CVIP2
Datasheet
SAA7115
Date:
Version:
10/23/01
0.67
2.5 Clock Generation
On-Chip Line Locked Clock Generation according ITU601
Generation of a frame locked Audio Master Clock to support a constant number of audio clocks per video field.
Second onboard analog PLL to be used for:
– On-Chip Line Locked Square Pixel Clock Generation for PAL and NTSC Square Pixel Video Output or
– optionally Generation of a low jitter frame locked Audio Clock from the Audio Master Clock through reuse of the
analog Square Pixel PLL. Supported audio clock frequencies are 256*fs, 384*fs and 512*fs (fs = 32 KHz, 44.1 KHz
or 48 KHz).
2.6 General Features
CMOS 3.3 V device with 5 V tolerant digital inputs and I/O ports
Programming via serial I2C-bus, full read-back ability by an external controller, bit rate up to 400 kbit/s
Software controlled power saving stand-by modes
Boundary Scan Test circuit complies to the IEEE Std. 1149.b1 -1994
Confidential - NDA required
Filename: SAA7115_Datasheet.fm
page 8
Last edited by H. Lambers
 

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