The FID flag is used to determine whether the first or second field of a frame is going to be processed within the scaler
and it is used as trigger condition for the task handling (see bits STRC[1:0] 90H[1:0]).
According to ITU 656, when FID is at logic 0 means first field of a frame. To ease the application, the polarities of the
detection results on the X-port signals and the internal decoder ID can be changed via XFDH.
As the V-sync from the decoder path has a half line timing (due to the interlaced video signal), but the scaler processing
only knows about full lines, during 1st fields from the decoder the line count of the scaler possibly shifts by one line,
compared to the 2nd field. This can be compensated for by switching the V-trigger event, as defined by XDV0, to the
opposite V-sync edge or by using the vertical scalers phase offsets. The vertical timing of the decoder can be seen in
Figs 22 and 23.
As the H and V reference events inside the ITU 656 data stream (from X-port) and the real-time reference signals from
the decoder path are processed differently, the trigger events for the input acquisition also have to be programmed
Table 11 Processing trigger and start
Internal decoder: The processing triggers at the reference edge of the V123 pulse
(see Figs 22 (50 Hz) and 23 (60 Hz)), and starts earliest with the rising edge of the
decoder HREF at line number:
falling edge: 4/7 (50/60 Hz, 1st field), resp. 3/6 (50/60 Hz, 2nd field) (decoder count)
rising edge: 2/5 (50/60 Hz, 1st field), resp. 2/5 (50/60 Hz, 2nd field) (decoder count)
External ITU 656 stream: The processing starts earliest with SAV at line number 23
(50 Hz system), respectively line 20 (60 Hz system) (according to ITU 656 count)
18.104.22.168 Task handling
The task handler controls the switching between the two programming register sets. The main function is controlled by
subaddresses 90H and C0H.
The operational modes of the task handler are controlled by the bits CMOD[80H] and FMOD[9bH].
A task is enabled via the global control bits TEA[80H] and TEB[80H].
The handler is then triggered by events, which can be defined for each register set.
In case of a programming error the task handling and the complete scaler can be reset to the initial states by setting the
software reset bit SWRST[88H] to logic 0. Especially if the programming registers, related acquisition window and
scale are reprogrammed while a task is active, a software reset MUST be performed after programming.
Contrary to the disabling/enabling of a task, which is evaluated at the end of a running task, when SWRST is at logic 0
it sets the internal state machines directly to their idle states.
The basic operation of the task handler is strongly orientated on the window definitions, which means, if a starting point
(in terms of XO and YO values) is missed, or the window definition (especially in terms of the (YO + YS) value) is larger
than the input field, the operation is inhibited or incoming video fields are skipped.
To better support non standard input signals and signal sources with varying field lengths (like a VCR in fast
forward/rewind mode), there are now some different operational modes implemented for the task handling.
Field Mode (bit FMOD [9BH])
This is a task specific bit (for flexibility reasons), but normally both tasks should be programmed to the same value.
If the FMOD bit is set to ‘1’ the YO and YS parameters change the meaning.
YO defines the start line and YS the end line (instead of the window length) for the scalers processing window.
Additionally the trigger conditions of the task handler are changed.
Conﬁdential - NDA required
Last edited by H. Lambers