Philips Semiconductors
CS-PD Hamburg
CVIP2
Datasheet
SAA7115
Date:
Version:
10/23/01
0.67
CVBS input
expansion port
data output
burst
processing delay ADC to expansion port:
140 × 1/LLC
sync clipped
HREF (50 Hz)
CREF
720 × 2/LLC
CREF2
HS (50 Hz)
5 × 2/LLC
programming range 108
0
(step size: 8/LLC)
HREF (60 Hz)
CREF
720 × 2/LLC
CREF2
HS (60 Hz)
1 × 2/LLC
programming range 107
(step size: 8/LLC)
0
12 × 2/LLC
144 × 2/LLC
2 × 2/LLC
−107
16 × 2/LLC
138 × 2/LLC
2 × 2/LLC
−106
MHB542
The signals HREF, HS, CREF2 and CREF are available on pins RTS0 and/or RTS1. Their polarity can be inverted via RTP0
and/or RTP1 (see Section 16.2: Tables 69, 70 and 71)
The signals HREF and HS are available on pin XRH (see Section 16.2 Table 72).
Fig.24 Horizontal timing diagram (50/60 Hz).
Confidential - NDA required
Filename: SAA7115_Datasheet.fm
page 48
Last edited by H. Lambers