8.1.5 POWER-ON RESET AND CHIP ENABLE (CE) INPUT
A missing clock, insufficient digital or analog VDDA0 supply voltages (below 2.8 V) will start the reset sequence; all outputs
are forced to 3-state (see Fig.21). The indicator output RES is LOW for approximately 128 LLC after the internal reset
and can be applied to reset other circuits of the digital TV system.
It is possible to force a reset by pulling the Chip Enable pin (CE) to ground. After the rising edge of CE and sufficient
power supply voltage, the outputs LLC, LLC2 and SDA return from 3-state to active, while the other signals have to be
activated via programming.
However, some external devices require an active clock during reset to avoid hang up. For these applications it is
possible to activate both the I-port and/or the X-port outputs by pulling the ITRI- and/or XTRI inputs to logic 1 by an
external pull up resistor (4.7 kΩ).
In detail: Pulling ITRI to 1 activates the outputs ICLK, IPD[7:0], IDQ, IGPH, IGPV, IGP0 and IGP1; pulling XTRI to 1
activates the outputs XCLK, XPD[7:0], XDQ, XRH and XRV. During reset both ICLK and XCLCK deliver the LLC-clock
(27 MHz) generated by the internal decoder PLL.
If ITRI and/or XTRI are not connected, an internal pull up resistor takes care that these pins remain in 3-state.
In any case it is possible to force these ports to 3-state by setting XPE[1:0] and/or IPE[1:0] to 00.
Conﬁdential - NDA required
Last edited by H. Lambers