Philips Semiconductors
CS-PD Hamburg
CVIP2
Datasheet
SAA7115
Date:
Version:
10/23/01
0.67
The LFCO signal is multiplied by a factor of 2 and 4 in the internal PLL circuit (including phase detector, loop filtering,
VCO and frequency divider) to obtain the output clock signals. The rectangular output clocks have a 50% duty factor.
Table 5 Decoder clock frequencies
CLOCK
XTALO
LLC
LLC2
LLC4 (INTERNAL)
LLC8 (VIRTUAL)
FREQUENCY (MHz)
24.576 OR 32.110
27
13.5
6.75
3.375
LFCO
BAND PASS
FC = LLC/4
ZERO
CROSS
DETECTION
PHASE
DETECTION
LOOP
FILTER
OSCILLATOR
LLC
DIVIDER
1/2
DIVIDER
1/2
MHB330
LLC2
Fig.20 Block diagram of the clock generation circuit.
Confidential - NDA required
Filename: SAA7115_Datasheet.fm
page 40
Last edited by H. Lambers