Philips Semiconductors
CS-PD Hamburg
CVIP2
Datasheet
SAA7115
ANALOG INPUT
ADC
NO BLANKING ACTIVE
1
0
VBLK
<- CLAMP
1
0
HCL
GAIN ->
1
0
HSY
Date:
Version:
10/23/01
0.67
1
0
CLL
0
1
SBOT
1
0
WIPE
+ CLAMP
− CLAMP NO CLAMP + GAIN
− GAIN fast − GAIN
WIPE = white peak level (510).
SBOT = sync bottom level (1).
CLL = clamp level [120 for CVBS, Y(C), S; 256 for C(Y), PB-PR; 32 for RGB, Y].
HSY = horizontal sync pulse.
HCL = horizontal clamp pulse.
Fig.9 Clamp and gain flow chart.
slow + GAIN
MGC647
Confidential - NDA required
Filename: SAA7115_Datasheet.fm
page 27
Last edited by H. Lambers