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SAA7115 View Datasheet(PDF) - Philips Electronics

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SAA7115 Datasheet PDF : 214 Pages
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Philips Semiconductors
CS-PD Hamburg
CVIP2
Datasheet
SAA7115
Date:
Version:
10/23/01
0.67
8.1.1.1 Clamping
The clamp control circuit controls the correct clamping of the analog input signals. The coupling capacitor is also used
to store and filter the clamping voltage. An internal digital clamp comparator generates the information with respect to
clamp-up or clamp-down. The clamping levels for the two ADC channels are fixed for luminance (120),
chrominance (256) and for component inputs as component Y (32), components PB and PR (256). The clamping time is
defined by the internally generated HCL pulse on the back porch of the video signal.
8.1.1.2 Gain control
The gain control circuit receives (via the I2C-bus) the static gain levels for the two analog amplifiers or controls one of
these amplifiers automatically via a built-in Automatic Gain Control (AGC) as part of the Analog Input Control (AICO).
The AGC (automatic gain control for luminance) is used to amplify a CVBS or Y signal to the required signal amplitude,
matched to the ADCs input voltage range. The AGC active time is the sync bottom of the video signal and is defined by
the internally generated HSY pulse.
Signal (white) peak control limits the gain at signal overshoots. The flow charts (see Figs 8 and 9) show more details of
the AGC. The influence of supply voltage variation within the specified range is automatically eliminated by clamp and
automatic gain control.
handbook, halfpage
511
120
1
TV line
analog line blanking
GAIN CLAMP
HSY
HCL
MHB726
Fig.5 Analog line with clamp (HCL) and gain
range (HSY).
Confidential - NDA required
Filename: SAA7115_Datasheet.fm
page 23
Last edited by H. Lambers
 

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