S80296SA50 View Datasheet(PDF) - Intel

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S80296SA50

COMMERCIAL CHMOS 16-BIT MICROCONTROLLER

Intel 

80296SA COMMERCIAL CHMOS 16-BIT MICROCONTROLLER

tics” is Section 6.0; “Errata” is Section 8.0, and “Datasheet Revision History” is Section 9.0.

6. Table 2 was changed to Table 1 and the “process information” was corrected to show that “no mark” sig-

nifies a CHMOS process.

7. Table 3 was changed to Table 7 and several clarifications were made.

8. Figure 3 was changed to correct the product name. Pin assignments did not change.

9. Table 4 was changed to Table 2 and pin 3 was changed from “no connection” to “tie to VCC.”

10. Figure 4 was changed to correct the product name. Pin assignments did not change.

11. Figure 5, “ICC versus Frequency in Reset,” was added. Remaining figure numbers were incremented.

12. Table 6 was changed to Table 4 and a note for handling the “no connection” pins was added.

13. Table 8 was changed to Table 6. The descriptions of BREQ#, HLDA#, and HOLD# were changed to

reflect their operation during hold. The description of the ONCE signal was changed to reflect the correct

states of READY, RESET#, and NMI during ONCE mode. The description of PLLEN2:1 was changed to

show the correct pin states to achieve each phase-locked loop (PLL) clock multiplier mode. The descrip-

tions of RPD and RESET# were changed to reflect system requirements when using the PLL.

14. Two notes were added to clarify the “Operating Conditions” in the “Electrical Characteristics” section.

15. Table 9 was changed to Table 8, the notes were re-ordered, and the following specifications were

changed:

• ICC max was changed to 150 mA

(from 120 mA).

• VOH min was changed to VCC–0.5 V

(from VCC–0.3 V) at IOH = –200µA.

• VOH min was changed to VCC–0.9 V

(from VCC–0.7V) at IOH = –3.2 mA.

• Test condition for VOL1 max = 0.45 V was changed to IOL = 8 mA (from IOL = 10 mA).

• RRST min and max were changed to 50 kΩ and 150 kΩ (from 9 kΩ and 95 kΩ).

• VOH3 min specification was added.

16. Table 10 was divided into two tables: timing specifications that the microcontroller will meet (Table 10)

and those that the external memory system must meet (Table 11). Note 7 was deleted and the remain-

ing notes were re-ordered. The following specifications were changed or added in Table 10:

• FXTAL1 min for the PLL in 4x mode was changed to 8 MHz (from 4 MHz); a clarifying note was added.

• TXHCH min was changed to 3 ns (from TBD).

• TLLAX min was changed to 1 ns (from TBD).

• TLLRL min was changed to 3 ns (from TBD)

• TRHAX min was changed to t – 4 ns (from t).

• TAVWL min (2t – 25) was added to Table 10.

• TSLDV min (4t – 28) was added to Table 11.

17. Table 11 was divided into two tables: timing specifications that the microcontroller will meet (Table 12)

and those that the external memory system must meet (Table 13). Note 7 was deleted and the remain-

ing notes were re-ordered. The following specifications were changed:

• FXTAL1 min for the PLL in 4x mode was changed to 8 MHz (from 4 MHz); a clarifying note was added.

• TWHQX min was changed to t – 5 ns (from t – 2 ns).

18. Figure 6 was changed to show the correct PLLEN2:1 values to select the 2x clock multiplier mode.

19. Table 13 was changed to Table 15 and a note was added.

20. Table 14 was changed to Table 16, 1/TXLXL specifications for each phase-locked loop (PLL) mode were

added, and Note 2 was deleted.

34

PRELIMINARY

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