S80296SA-50 View Datasheet(PDF) - Intel
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S80296SA-50 Datasheet PDF : 40 Pages
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80296SA COMMERCIAL CHMOS 16-BIT MICROCONTROLLER
6.2.4 AC CHARACTERISTICS — DEMULTIPLEXED BUS MODE
Test Conditions: Capacitive load on all pins = 50 pF, Rise and Fall Times = 3 ns.
Table 10. AC Characteristics the 80C296SA Will Meet, Demultiplexed Bus Mode
Symbol
Parameter
Min
Max
Units
FXTAL1
Frequency on XTAL1, PLL in 1x mode
Frequency on XTAL1, PLL in 2x mode
16
8 (2)
50 (1)
25
MHz
MHz
Frequency on XTAL1, PLL in 4x mode
8 (2)
12.5
MHz
f
Operating frequency, f = FXTAL1; PLL in 1x mode
Operating frequency, f = 2FXTAL1; PLL in 2x mode
Operating frequency, f = 4FXTAL1; PLL in 4x mode
t
Period, t = 1/f
16
50
MHz
20
62.5
ns
TAVWL
Address Valid to WR# Falling Edge
t – 10
ns
TAVRL
Address Valid to RD# Falling Edge
t – 10
ns
TRHRL
Read High to Next Read Low
t–5
ns
TXHCH
XTAL1 High to CLKOUT High or Low
3
50
ns
TCLCL
CLKOUT Cycle Time
2t
ns
TCHCL
CLKOUT High Period
t – 10
t + 15
ns
TCLLH
CLKOUT Falling Edge to ALE Rising Edge
–13
10
ns
TLLCH
ALE Falling Edge to CLKOUT Rising Edge
–15
15
ns
TLHLH
ALE Cycle Time
4t
ns (3,4)
TLHLL
ALE High Period
t – 10
t + 10
ns
TRLCL
RD# Low to CLKOUT Falling Edge
–5
11
ns
TRLRH
RD# Low Period
3t – 18
ns (3)
TRHLH
RD# Rising Edge to ALE Rising Edge
t–4
t + 15
ns (4)
TWLCL
WR# Low to CLKOUT Falling Edge
–8
9
ns
TQVWH
Data Stable to WR# Rising Edge
3t – 10
ns (4)
TCHWH
CLKOUT High to WR# Rising Edge
–11
10
ns
TWLWH
WR# Low Period
3t – 10
ns (3)
TWHQX
Data Hold after WR# Rising Edge
t–5
t + 20
ns
TWHLH
WR# Rising Edge to ALE Rising Edge
t–5
t + 10
ns (3)
NOTES:
1. 25 MHz is the maximum input frequency when using an external crystal oscillator; however, 50 MHz
can be applied with an external clock source.
2. When the phase-locked loop (PLL) circuitry is enabled, the minimum input frequency on XTAL1 is 8
MHz. The PLL cannot be run at frequencies lower than 16 MHz.
3. If using either READY or BUSCONx to insert wait states, add 2t × n, where n = number of wait states.
4. Assuming back-to-back bus cycles.
24
PRELIMINARY
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