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80C296SA View Datasheet(PDF) - Intel

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80C296SA Datasheet PDF : 40 Pages
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80296SA COMMERCIAL CHMOS 16-BIT MICROCONTROLLER
6.2.3 AC CHARACTERISTICS — MULTIPLEXED BUS MODE
Test Conditions: Capacitive load on all pins = 50 pF, Rise and Fall Times = 3 ns.
Table 8. AC Characteristics the 80C296SA Will Meet, Multiplexed Bus Mode
Symbol
Parameter
Min
Max
Units
FXTAL1
Frequency on XTAL1, PLL in 1x mode
Frequency on XTAL1, PLL in 2x mode
16
8 (2)
50 (1)
25
MHz
MHz
Frequency on XTAL1, PLL in 4x mode
8 (2)
12.5
MHz
f
Operating frequency, f = FXTAL1; PLL in 1x mode
Operating frequency, f = 2FXTAL1; PLL in 2x mode
Operating frequency, f = 4FXTAL1; PLL in 4x mode
t
Period, t = 1/f
16
50
MHz
20
62.5
ns
TXHCH
XTAL1 Rising Edge to CLKOUT High or Low
3
50
ns
TCLCL
CLKOUT Cycle Time
2t
ns
TCHCL
CLKOUT High Period
t – 10
t + 15
ns
TAVWL
Address Valid to WR# Falling Edge
2t – 25
ns
TCLLH
CLKOUT Falling Edge to ALE Rising Edge
–13
10
ns
TLLCH
ALE Falling Edge to CLKOUT Rising Edge
–15
15
ns
TLHLH
ALE Cycle Time
4t
ns (3)
TLHLL
ALE High Period
t – 10
t + 10
ns
TAVLL
Address Valid to ALE Falling Edge
t – 15
ns
TLLAX
Address Hold after ALE Falling Edge
1
ns
TLLRL
ALE Falling Edge to RD# Falling Edge
3
ns
TRLCL
RD# Low to CLKOUT Falling Edge
–10
20
ns
TRLRH
RD# Low Period
2t 25
ns (3)
TRHLH
RD# Rising Edge to ALE Rising Edge
t–5
t + 15
ns (4)
TRLAZ
RD# Low to Address Float
5
ns
TLLWL
ALE Falling Edge to WR# Falling Edge
4
ns
TQVWH
Data Stable to WR# Rising Edge
2t – 27
ns (3)
TCHWH
CLKOUT High to WR# Rising Edge
–15
5
ns
TWLWH
WR# Low Period
2t – 25
ns (3)
NOTES:
1. 25 MHz is the maximum input frequency when using an external crystal oscillator; however, 50 MHz
can be applied with an external clock source.
2. When the phase-locked loop (PLL) circuitry is enabled, the minimum input frequency on XTAL1 is 8
MHz. The PLL cannot be run at frequencies lower than 16 MHz.
3. If wait states are used, add 2t × n, where n = number of wait states.
4. Assuming back-to-back bus cycles.
5. 8-bit bus only.
20
PRELIMINARY
 

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