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S80296SA50 View Datasheet(PDF) - Intel

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S80296SA50 Datasheet PDF : 40 Pages
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PRELIMINARY
80296SA COMMERCIAL
CHMOS 16-BIT MICROCONTROLLER
s 50 MHz Operation
s 6 Mbytes of Linear Address Space
s 512 Bytes of Register RAM
s 2 Kbytes of Code/Data RAM
s Register-register Architecture
s Footprint and Functionally Compatible
Upgrade for the 8XC196NP and
80C196NU
s Optional Phase-locked Loop (PLL)
Circuitry with 2x or 4x Clock Multiplier
s 32 I/O Port Pins
s 19 Interrupt Sources, 14 with
Programmable Priorities
s 4 External Interrupt Pins and NMI Pin
s 2 Flexible 16-bit Timer/Counters with
Quadrature Counting Capability
s 3 Pulse-width Modulator (PWM)
Outputs with High Drive Capability
s Full-duplex Serial Port with Dedicated
Baud-rate Generator
40 MHz standard; 50 MHz is Speed Premium
s Chip-select Unit
— 6 Chip-select Pins
— Dynamic Demultiplexed/Multiplexed
Address/Data Bus for Each
Chip Select
— Programmable Wait States
(0–15) for Each Chip Select
— Programmable Bus Width
(8- or 16-bit) for Each Chip Select
— Programmable Address Range for
Each Chip Select
s Event Processor Array (EPA) with
4 High-speed Capture/Compare
Channels
s Multiply and Accumulate Executes in
80 ns Using the 40-bit Hardware
Accumulator
s 880 ns 32/16 Unsigned Division
s 100-pin QFP Package
s Complete System Development
Support
s High-speed CHMOS Technology
The 80296SA is a member of Intel’s 16-bit MCS® 96 microcontroller family. The 80296SA features 6 Mbytes
of linear address space, a demultiplexed bus, and a chip-select unit. The external bus can dynamically switch
between multiplexed and demultiplexed operation. The device has hardware and instructions to support
various digital signal processing algorithms.
NOTE
This datasheet contains information on new products in production. The specifications
are subject to change without notice. Verify with your local Intel sales office that you have
the latest datasheet before finalizing a design.
COPYRIGHT © INTEL CORPORATION, 1997
January 1997
Order Number: 272748-003
 

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