PRODUCT OVERVIEW
S3C2400 RISC MICROPROCESSOR
Register Name
USB DEVICE
FUNC_ADDR_REG
PWR_REG
INT_REG
INT_MASK_REG
FRAME_NUM_REG
RESUME_CON_REG
EP0_CSR
EP0_MAXP
EP0_OUT_CNT
EP0_FIFO
EP1_IN_CSR
EP1_IN_MAXP
EP1_FIFO
EP2_IN_CSR
EP2_IN_MAXP
EP2_FIFO
EP3_OUT_CSR
EP3_OUT_MAXP
EP3_OUT_CNT
EP3_FIFO
EP4_OUT_CSR
EP4_OUT_MAXP
EP4_OUT_CNT
EP4_FIFO
DMA_CON
DMA_UNIT
DMA_FIFO
DMA_TX
TEST_MODE
IN_CON_REG
Table 1-4. S3C2400 Special Registers (Continued)
Address
(B. Endian)
Address
(L. Endian)
Acc. Read/W
Unit
rite
Function
0x15200140
←
0x15200144
0x15200148
0x1520014c
0x15200150
0x15200154
0x15200160
0x15200164
0x15200168
0x1520016c
0x15200180
0x15200184
0x15200188
0x15200190
0x15200194
0x15200198
0x152001a0
0x152001a4
0x152001a8
0x152001ac
0x152001b0
0x152001b4
0x152001b8
0x152001bc
0x152001c0
0x152001c4
0x152001c8
0x152001cc
0x152001f4
0x152001f8
W
R/W Function Address
Power Management
R Interrupt Pending and Clear
R/W Interrupt Mask
R Frame Number
R/W Resume Signal Control
Clock Generator Control
End Point0 MAX Packet
End Point0 Out Write Count
End Point0 FIFO Read/Write
End Point1 in Control Status
End Point1 in MAX Packet
W End Point2 FIFO Write
R/W End Point2 in Control Status
End Point2 in MAX Packet
W End Point2 FIFO Write
R/W End Point3 Out Control Status
End Point3 Out MAX Packet
R End Point3 Out Write Count
End Point3 FIFO Read
R/W End Point4 Out Control Status
End Point4 Out MAX Packet
R End Point4 Out Write Count
End Point4 FIFO Read
R/W DMA Interface Control
DMA Transfer Unit Counter
DMA Transfer FIFO Counter
DMA Total Transfer Counter
W Test Mode Control
In Packet Number Control
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