S25FL128K View Datasheet(PDF) - Spansion Inc.
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S25FL128K Datasheet PDF : 59 Pages
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Data Sheet (Preliminary)
6.2.33
Erase Security Registers (44h)
The S25FL128K offers three 256-byte Security Registers which can be erased and programmed individually.
These registers may be used by the system manufacturers to store security and other important information
separately from the main memory array.
The Erase Security Register instruction is similar to the Sector Erase instruction. A Write Enable instruction
must be executed before the device will accept the Erase Security Register Instruction (Status Register bit
WEL must equal 1). The instruction is initiated by driving the CS# pin low and shifting the instruction code
“44h” followed by a 24-bit address (A23-A0) to erase one of the three security registers.
ADDRESS
Security Register #1
Security Register #2
Security Register #3
A23-16
00h
00h
00h
A15-12
0001
0010
0011
A11-8
0000
0000
0000
A7-0
Don’t Care
Don’t Care
Don’t Care
The Erase Security Register instruction sequence is shown in Figure 6.39. The CS# pin must be driven high
after the eighth bit of the last byte has been latched. If this is not done the instruction will not be executed.
After CS# is driven high, the self-timed Erase Security Register operation will commence for a time duration
of tSE (see AC Electrical Characteristics on page 54). While the Erase Security Register cycle is in progress,
the Read Status Register instruction may still be accessed for checking the status of the BUSY bit. The BUSY
bit is a 1 during the erase cycle and becomes a 0 when the cycle is finished and the device is ready to accept
other instructions again. After the Erase Security Register cycle has finished the Write Enable Latch (WEL) bit
in the Status Register is cleared to 0. The Security Register Lock Bits (LB3:1) in the Status Register-2 can be
used to OTP protect the security registers. Once a lock bit is set to 1, the corresponding security register will
be permanently locked, and an Erase Security Register instruction to that register will be ignored (see
Security Register Lock Bits (LB3, LB2, LB1) on page 14).
Figure 6.39 Erase Security Registers Instruction Sequence
CS#
Mode 3
CLK Mode 0
SI
0 1 23 4 5 6 78 9
29 30 31 Mode 3
Mode 0
Instruction (44h)
24-bit Address
23 22
21 0
High Impedance
SO
= MSB
April 1, 2011 S25FL128K_00_02
S25FL128K
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