S25FL128K View Datasheet(PDF) - Spansion Inc.

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S25FL128K

128-Mbit CMOS 3.0 Volt Flash Memory with 104-MHz SPI (Serial Peripheral Interface) Multi I/O Bus

Spansion Inc. 

Data Sheet (Preliminary)

Figure 6.25 32 kB Block Erase Instruction Sequence Diagram

CS#

Mode 3

CLK Mode 0

0123456789

29 30 31 Mode 3

Mode 0

Instruction (52h)

24-Bit Address

SIO

23 22

210

SO

= MSB

High Impedance

6.2.21

64 KB Block Erase (D8h)

The Block Erase instruction sets all memory within a specified block (64 kbytes) to the erased state of all 1s

(FFh). A Write Enable instruction must be executed before the device will accept the Block Erase Instruction

(Status Register bit WEL must equal 1). The instruction is initiated by driving the CS# pin low and shifting the

instruction code “D8h” followed a 24-bit block address (A23-A0) See Block Diagram on page 8. The Block

Erase instruction sequence is shown in Figure 6.26.

The CS# pin must be driven high after the eighth bit of the last byte has been latched. If this is not done the

Block Erase instruction will not be executed. After CS# is driven high, the self-timed Block Erase instruction

will commence for a time duration of tBE (see See AC Electrical Characteristics on page 54.). While the Block

Erase cycle is in progress, the Read Status Register instruction may still be accessed for checking the status

of the BUSY bit. The BUSY bit is a 1 during the Block Erase cycle and becomes a 0 when the cycle is finished

and the device is ready to accept other instructions again. After the Block Erase cycle has finished the Write

Enable Latch (WEL) bit in the Status Register is cleared to 0. The Block Erase instruction will not be executed

if the addressed page is protected by the Block Protect (CMP, SEC, TB, BP2, BP1, and BP0) bits. See

Table 6.2, Status Register Memory Protection (CMP = 0) on page 15.

Figure 6.26 64 kB Block Erase Instruction Sequence Diagram

CS#

Mode 3

CLK Mode 0

SI

0 1 2 3 4 5 6 78 9

29 30 31 Mode 3

Mode 0

Instruction (D8h)

24-Bit Address

23 22

21 0

SO

= MSB

High Impedance

6.2.22

Chip Erase (C7h / 60h)

The Chip Erase instruction sets all memory within the device to the erased state of all 1s (FFh). A Write

Enable instruction must be executed before the device will accept the Chip Erase Instruction (Status Register

bit WEL must equal 1). The instruction is initiated by driving the CS# pin low and shifting the instruction code

“C7h” or “60h”. The Chip Erase instruction sequence is shown in Figure 6.27.

The CS# pin must be driven high after the eighth bit has been latched. If this is not done the Chip Erase

instruction will not be executed. After CS# is driven high, the self-timed Chip Erase instruction will commence

April 1, 2011 S25FL128K_00_02

S25FL128K

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