datasheetbank_Logo
Integrated circuits, Transistor, Semiconductors Search and Datasheet PDF Download Site

S25FL128K View Datasheet(PDF) - Spansion Inc.

Part Name
Description
View to exact match
S25FL128K Datasheet PDF : 59 Pages
First Prev 21 22 23 24 25 26 27 28 29 30 Next Last
Data Sheet (Preliminary)
Figure 6.13 Fast Read Dual I/O Instruction Sequence (Previous instruction set M5-4 = 10)
CS#
Mode 3 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
CLK Mode 0
IO0
6 4 20 6 4 2 0 6 4 2 0 6 4
IO1
7 5 3 1 7 5 3 1 7 5 3 1 75
A23-16
A15-8
A7-0
M7-0
CS#
15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
CLK
IO Switches from Input to Output
IO0
6 4 20 6 4 2 0 6 4 2 0 6 4 2 0 6
IO1
7531 75 31 753 1 7531 7
Byte 1
Byte 2
Byte 3
Byte 4
6.2.11
Fast Read Quad I/O (EBh)
The Fast Read Quad I/O (EBh) instruction is similar to the Fast Read Dual I/O (BBh) instruction except that
address and data bits are input and output through four pins IO0, IO1, IO2 and IO3 and four Dummy clock are
required prior to the data output. The Quad I/O dramatically reduces instruction overhead allowing faster
random access for code execution (XIP) directly from the Quad SPI. The Quad Enable bit (QE) of Status
Register-2 must be set to enable the Fast Read Quad I/O Instruction.
Fast Read Quad I/O with “Continuous Read Mode”
The Fast Read Quad I/O instruction can further reduce instruction overhead through setting the “Continuous
Read Mode” bits (M7-0) after the input Address bits (A23-0), as shown in Figure 6.14, Fast Read Quad I/O
Instruction Sequence (Initial instruction or previous M5-4 10) on page 28. The upper nibble of the (M7-4)
controls the length of the next Fast Read Quad I/O instruction through the inclusion or exclusion of the first
byte instruction code. The lower nibble bits of the (M3-0) are don’t care (“x”). However, the IO pins should be
high-impedance prior to the falling edge of the first data out clock.
If the “Continuous Read Mode” bits M5-4 = (1,0), then the next Fast Read Quad I/O instruction (after CS# is
raised and then lowered) does not require the EBh instruction code, as shown in Figure 6.15, Fast Read
Quad I/O Instruction Sequence (Previous instruction set M5-4 = 10) on page 28. This reduces the instruction
sequence by eight clocks and allows the Read address to be immediately entered after CS# is asserted low.
If the “Continuous Read Mode” bits M5-4 do not equal to (1,0), the next instruction (after CS# is raised and
then lowered) requires the first byte instruction code, thus returning to normal operation. A “Continuous Read
Mode” Reset instruction can also be used to reset (M7-0) before issuing normal instructions (see
Section 6.2.16, Continuous Read Mode Reset (FFh or FFFFh) on page 33).
April 1, 2011 S25FL128K_00_02
S25FL128K
27
 

Share Link: 

datasheetbank.com [ Privacy Policy ] [ Request Datasheet ] [ Contact Us ]