S25FL064K View Datasheet(PDF) - Spansion Inc.
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S25FL064K Datasheet PDF : 66 Pages
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Data Sheet
7.8
Fast Read Dual Output (3Bh)
The Fast Read Dual Output (3Bh) instruction is similar to the standard Fast Read (0Bh) instruction except that
data is output on two pins; IO0 and IO1. This allows data to be transferred from the S25FL064K at twice the
rate of standard SPI devices. The Fast Read Dual Output instruction is ideal for quickly downloading code
from Flash to RAM upon power-up or for applications that cache code-segments to RAM for execution.
Similar to the Fast Read instruction, the Fast Read Dual Output instruction can operate at the highest
possible frequency of FR (see See AC Electrical Characteristics on page 61.). This is accomplished by
adding eight “dummy” clocks after the 24-bit address as shown in Figure 7.8. The dummy clocks allow the
device's internal circuits additional time for setting up the initial address. The input data during the dummy
clocks is “don’t care”. However, the IO0 pin should be high-impedance prior to the falling edge of the first data
out clock.
Figure 7.8 Fast Read Dual Output Instruction Sequence Diagram
CS
Mode 3
CLK Mode 0
0 1 2 3 4 5 6 7 8 9 10
28 29 30 31
Instruction (3Bh)
24-Bit Address
IO0
23 22 21 3 2 1 0
IO1
CS
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55
CLK
Dummy Clocks
IO_0 Switches from Input to Output
IO0
6 4 2 0 6 4 2 06 4 2 0 6 4 2 06
IO1
= MSB
753 17 53 1753 17 53 17
Data Out 1
Data Out 2
Data Out 3
Data Out 4
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S25FL064K
S25FL064K_00_03 July 13, 2011
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