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S25FL064K View Datasheet(PDF) - Spansion Inc.

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Data Sheet
7.4
Read Status Register-1 (05h) and Read Status Register-2 (35h)
The Read Status Register instructions allow the 8-bit Status Registers to be read. The instruction is entered
by driving CS# low and shifting the instruction code “05h” for Status Register-1 or “35h” for Status Register-2
into the SI pin on the rising edge of CLK. The status register bits are then shifted out on the SO pin at the
falling edge of CLK with most significant bit (MSB) first as shown in Figure 7.4. The Status Register bits are
shown in Figure 6.1 and Figure 6.2 and include the BUSY, WEL, BP2-BP0, TB, SEC, SRP0, SRP1, QE,
LB3-1, CMP and SUS bits (see Section 6.1, Status Register on page 15).
The Read Status Register instruction may be used at any time, even while a Program, Erase or Write Status
Register cycle is in progress. This allows the BUSY status bit to be checked to determine when the cycle is
complete and if the device can accept another instruction. The Status Register can be read continuously, as
shown in Figure 7.4. The instruction is completed by driving CS# high.
Figure 7.4 Read Status Register Instruction Sequence Diagram
CS#
Mode 3
CLK Mode 0
SI
SO
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
Instruction (05h or 35h)
High Impedance
Status Register 1 or 2 Out
Status Register 1 or 2 Out
76 54 321 0 76 54 321 0 7
= MSB
7.5
Write Status Register (01h)
The Write Status Register instruction allows the Status Register to be written. Only non-volatile Status
Register bits SRP0, SEC, TB, BP2, BP1, BP0 (bits 7 thru 2 of Status Register-1) and CMP, LB3, LB2, LB1,
QE, SRP1 (bits 14 thru 8 of Status Register-2) can be written to. All other Status Register bit locations are
read-only and will not be affected by the Write Status Register instruction. LB3-1 are non-volatile OTP bits;
once each is set to 1, it can not be cleared to 0. The Status Register bits are shown in Figure 6.1 and
Figure 6.2 on page 17, and described Section 6.1, Status Register on page 15.
To write non-volatile Status Register bits, a standard Write Enable (06h) instruction must previously have
been executed for the device to accept the Write Status Register Instruction (Status Register bit WEL must
equal 1). Once write enabled, the instruction is entered by driving CS# low, sending the instruction code
“01h”, and then writing the status register data byte as illustrated in Figure 7.5.
To write volatile Status Register bits, a Write Enable for Volatile Status Register (50h) instruction must have
been executed prior to the Write Status Register instruction (Status Register bit WEL remains 0). However,
SRP1 and LB3, LB2, LB1 can not be changed from “1” to “0” because of the OTP protection for these bits.
Upon power off, the volatile Status Register bit values will be lost, and the non-volatile Status Register bit
values will be restored when power on again.
To complete the Write Status Register instruction, the CS# pin must be driven high after the eighth or
sixteenth bit of data that is clocked in. If this is not done the Write Status Register instruction will not be
executed. If CS# is driven high after the eighth clock the CMP, QE and SRP1 bits will be cleared to 0.
During non-volatile Status Register write operation (06h combined with 01h), after CS# is driven high, the
self-timed Write Status Register cycle will commence for a time duration of tW (see Section 8.6, AC Electrical
Characteristics on page 61). While the Write Status Register cycle is in progress, the Read Status Register
instruction may still be accessed to check the status of the BUSY bit. The BUSY bit is a 1 during the Write
Status Register cycle and a 0 when the cycle is finished and ready to accept other instructions again. After
the Write Status Register cycle has finished, the Write Enable Latch (WEL) bit in the Status Register will be
cleared to 0.
July 13, 2011 S25FL064K_00_03
S25FL064K
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