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S25FL064K View Datasheet(PDF) - Spansion Inc.

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S25FL064K Datasheet PDF : 66 Pages
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Data Sheet
7.2
Write Enable for Volatile Status Register (50h)
The non-volatile Status Register bits described in Section 6.1, Status Register on page 15 can also be written
to as volatile bits. This gives more flexibility to change the system configuration and memory protection
schemes quickly without waiting for the typical non-volatile bit write cycles or affecting the endurance of the
Status Register non-volatile bits. To write the volatile values into the Status Register bits, the Write Enable for
Volatile Status Register (50h) instruction must be issued prior to a Write Status Register (01h) instruction.
Write Enable for Volatile Status Register instruction (Figure 7.2) will not set the Write Enable Latch (WEL) bit,
it is only valid for the Write Status Register instruction to change the volatile Status Register bit values.
Figure 7.2 Write Enable for Volatile Status Register Instruction Sequence Diagram
CS#
Mode 3
CLK Mode 0
SI
SO
0 1 2 3 4 5 6 7 Mode 3
Mode 0
Instruction (50h)
High Impedance
7.3 Write Disable (04h)
The Write Disable instruction (Figure 6) resets the Write Enable Latch (WEL) bit in the Status Register to a 0.
The Write Disable instruction is entered by driving CS# low, shifting the instruction code “04h” into the SI pin
and then driving CS# high. Note that the WEL bit is automatically reset after Power-up and upon completion
of the Write Status Register, Erase/Program Security Registers, Page Program, Quad Page Program, Sector
Erase, Block Erase and Chip Erase instructions.
Figure 7.3 Write Disable Instruction Sequence Diagram
CS#
Mode 3
CLK Mode 0
SI
SO
0 12 34 56 7
Instruction (04h)
Mode 3
Mode 0
High Impedance
22
S25FL064K
S25FL064K_00_03 July 13, 2011
 

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