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S25FL064K View Datasheet(PDF) - Spansion Inc.

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S25FL064K Datasheet PDF : 66 Pages
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Data Sheet
7.1
Table 7.5 Instruction Set (ID, Security Instructions)
Instruction Name
BYTE 1
(CODE)
BYTE 2
BYTE 3
Release Power down / Device ID
ABh
dummy
dummy
Manufacturer/ Device ID (2)
90h
dummy
dummy
Manufacturer/Device ID by Dual
I/O
92h
A23-A8
A7-A0, M[7:0]
Manufacture/Device ID by Quad
I/O
94h
A23-A0, M[7:0]
xxxx, (MF[7:0],
ID[7:0])
JEDEC ID
9Fh
(MF7-MF0)
(ID15-ID8)
Manufacturer Memory Type
Read Unique ID
4Bh
dummy
dummy
Read SFDP Register
48h, 5Ah
00h
00h
Erase Security Registers (3)
44h
A23–A16
A15–A8
Program Security Registers (3)
42h
A23–A16
A15–A8
Read Security Registers (3)
48h
A23–A16
A15–A8
Notes:
1. The Device ID will repeat continuously until /CS terminates the instruction.
2. See Manufacturer and Device Identification table for Device ID information.
3. Security Register Address:
Security Register 1: A23-16 = 00h; A15-8 = 10h; A7-0 = byte address
Security Register 2: A23-16 = 00h; A15-8 = 20h; A7-0 = byte address
Security Register 3: A23-16 = 00h; A15-8 = 30h; A7-0 = byte address
BYTE 4
dummy
00h
(MF[7:0],
ID[7:0])
(MF[7:0],
ID[7:0], …)
(ID7-ID0)
Capacity
dummy
A7–A0
A7–A0
A7–A0
A7–A0
BYTE 5
(ID7-ID0) (1)
(MF7-MF0)
dummy
dummy
(D7-0)
dummy
BYTE 6
(ID7-ID0)
(ID63-ID0)
(D7-0)
(D7-0)
(D7-0)
Write Enable (06h)
The Write Enable instruction (Figure 7.1) sets the Write Enable Latch (WEL) bit in the Status Register to a 1.
The WEL bit must be set prior to every Page Program, Quad Page Program, Sector Erase, Block Erase, Chip
Erase, Write Status Register and Erase/Program Security Registers instruction. The Write Enable instruction
is entered by driving CS# low, shifting the instruction code “06h” into the Data Input (SI) pin on the rising edge
of CLK, and then driving CS# high.
Figure 7.1 Write Enable Instruction Sequence Diagram
CS#
Mode 3
CLK Mode 0
SI
SO
01 23 45
Instruction (06h)
6 7 Mode 3
Mode 0
High Impedance
July 13, 2011 S25FL064K_00_03
S25FL064K
21
 

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