RT8859M View Datasheet(PDF) - Richtek Technology

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RT8859M

Multi-Phase PWM Controller for CPU Core Power Supply

Richtek Technology 

RT8859M

IMONA pin. The resistor connected to the IMONA pin

determines the voltage gain of the IMONA output.

The current monitor indicator equation is shown as :

VIMONA

=

ILOAD

x

RDROOP x

RIMONFBA

RIMONA

(58)

Where ILOAD is the output load current, RDROOP is the

equivalent load line resistance, and RIMONA and RIMONFBA

are the current monitor current setting resistors.

In VR12/IMVP7 specification, the voltage signal of current

monitoring will be restricted by a maximum value. Platform

designers have to select RIMONA to meet the maximum

voltage of IMONA at full load. Find RIMONA and RIMONFBA

based on :

RIMONA = VIMONA(MAX)

RIMONFBA IMAX x RDROOP

(59)

where VIMONA(MAX) is the maximum voltage at full load,

and IMAX is the full load current of VR.

IMirror

Current Mirror

VFBA + 2(VISENA)

OLL EN

+

-

VFBA

VCCAXG_SENSE

IMONFBA RIMONFBA

IMONA RIMONA

Figure 22. AXG VR : Current Monitoring Circuit

When the droop function is disabled, VCCAXG_SENSE no

longer varies with output current, so the current monitoring

function is adaptively changed internally under this

situation. The equation will be rewritten as :

VIMONA, NO_DROOP

= 2 x ILOAD x RRDCR x RIMONA

RIMONFBA

(60)

RIMONA = VIMONA(MAX)

RIMONFBA 2 x IMAX x RDCR

(61)

The ADC circuit of the AXG VR monitors the voltage

variation at the IMONA pin from 0V to 3.3V, and this

voltage is decoded into digital format and stored into the

Output_Current register. The ADC divides 3.3V into 255

levels, so LSB = 3.3V/255 = 12.941mV. Platform

Copyright ©2012 Richtek Technology Corporation. All rights reserved.

www.richtek.com

46

designers should design VIMONA to be 3.3V at ICCMAXA.

For example, when load current = 50% x ICCMAXA,

VIMONA = 1.65V and Output_Current register = 7Fh.

The IMONA pin is an output of the internal operational

amplifier and sends out IMONA signal. When the data of

Output_Current register reaches 255d (when IMONA

voltage rises above 3.3V), the ALERT signal will be

asserted to low, which is so-called SVID ICCMAXA alert.

In the mean time, the AXG VR will assert the bit 2 data to

1 in Status_1 register. The ALERT assertion will be de-

asserted when the data of Output_Current register

decreases to 242d (when IMONA voltage falls under

3.144V). The bit 2 assertion of Status_1 register is latched

and can only be cleared when two criteria are met : the

data of Output_Current register decreases to 242d (when

IMONA voltage falls under 3.144V) and the GetReg

command is sent to the Status_1 register of the AXG VR.

Quick Response

Current Mirror

QR trigger

VDAC, AXG

+

-

IMirror

VCCAXG_SENSE

IMONFBA RIMONFBA

Figure 23. AXG VR : Quick Response Triggering Circuit

The AXG VR utilizes a quick response feature to support

heavy load current demand during instantaneous load

transient. The AXG VR monitors the current of the

IMONFBA pin, and this current is mirrored to internal quick

response circuit. At steady state, this mirrored current

will not trigger a quick response. When the VOUT, AXG voltage

drops abruptly due to load apply transient, the mirrored

current into quick response circuit will also increase

instantaneously. When the mirrored current

instantaneously rises above 5μA, quick response will be

triggered.

When quick response is triggered, the quick response

circuit will generate a quick response pulse. The internal

quick response pulse generation circuit is similar to the

on-time generation circuit. The only difference is the

QRSETA pin. The voltage at the QRSETA pin also

is a registered trademark of Richtek Technology Corporation.

DS8859M-05 July 2012

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