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RT8859M View Datasheet(PDF) - Richtek Technology

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RT8859M Datasheet PDF : 51 Pages
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RT8859M
Usually, R1a is set to equal RNTC (25°C) and R1b is selected
to linearize the NTC's temperature characteristic. For a
given NTC, the design procedure is to get R1b and R2
first, and then C1 and C2 next. According to equation (39),
to compensate the temperature variations of the sense
resistor, the error amplifier gain (AV) should have the same
temperature coefficient as RSENSE. Hence :
A V, HOT = RSENSE, HOT
A V, COLD RSENSE, COLD
(40)
From (37), Av can be obtained at any temperature (T°C)
as :
A V,
T°C
=
R2
R1a // RNTC, T°C
+ R1b
(41)
The standard formula for the resistance of NTC thermistor
as a function of temperature is given by :
{ ( ) ( ) } RNTC, T°C
= R25°C
e β⎡⎢⎣
1
T+273
1
298 ⎥⎦
(42)
where R25°C is the thermistor's nominal resistance at room
temperature, β is the thermistor's material constant in
Kelvins, and T is the thermistor actual temperature in
Celsius.
To calculate DCR value at different temperatures, use the
equation below :
DCRT°C = DCR25°C x [1+ 0.00393 x (T 25)]
(43)
where 0.00393 is the temperature coefficient of copper.
For a given NTC thermistor, solving equation (41) at room
temperature (25°C) yields
R2 = AV, 25°C x (R1b + R1a // RNTC, 25°C)
(44)
where AV, 25°C is the error amplifier gain at room temperature
and can be obtained from equation (39). R1b can be
obtained by substituting (44) to (40),
R1b =
RSENSE, HOT
RSENSE, COLD
x (R1a / /RNTC, HOT ) (R1a / /RNTC, COLD )
⎛⎜1
RSENSE, HOT
RSENSE, COLD
(45)
Droop Disable
The AXG VR's droop function can be enabled or disabled
with different connections of the QRSETA pin. The
connection of the QRSETA pin is usually a voltage divider
circuit which is described later in the Quick Response
section. Before POR, the RT8859M will source 80μA
current from the QRSETA pin to the external voltage divider
to determine the voltage level while the RT8859M is still
not powered on. Before POR, if the voltage at the QRSETA
pin is higher than 4.5V, the AXG VR will operate in droop-
enabled mode. If the voltage is lower than 3.2V, the AXG
VR will operate without droop function, which means at
the DC level of DAC voltage. For example, a 5V voltage
divided by two 1kΩ resistors connected to the QRSETA
pin generates 2.54V (5V/2 + 80μA x 1kΩ/2) before POR
and 2.5V (5V/2) after POR.
Loop Compensation
Optimized compensation of the AXG VR allows for best
possible load step response of the regulator's output. A
type-I compensator with one pole and one zero is adequate
for a proper compensation. Figure 17 shows the
compensation circuit. Prior design procedure shows how
to select the resistive feedback components for the error
amplifier gain. Next, C1 and C2 must be calculated for the
compensation. The target is to achieve constant resistive
output impedance over the widest possible frequency
range.
The pole frequency of the compensator must be set to
compensate the output capacitor ESR zero :
fP
=
2
x
π
1
xC
x
RC
(46)
where C is the capacitance of output capacitor, and RC is
the ESR of output capacitor. C2 can be calculated as
below :
C2 = C x RC
(47)
R2
The zero of compensator has to be placed at half of the
switching frequency to filter the switching related noise.
Such that,
( ) C1 =
1
R1b + R1a / /RNTC, 25°C x π x fSW
(48)
TON Setting
High frequency operation optimizes the application by
allowing smaller component size, but with the trade-off of
efficiency due to higher switching losses. This may be
acceptable in ultra portable devices where the load currents
Copyright ©2012 Richtek Technology Corporation. All rights reserved.
www.richtek.com
42
is a registered trademark of Richtek Technology Corporation.
DS8859M-05 July 2012
 

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