RT8856
PHASEx
ISENx
ISENx_N
VOUT
L
DCR
RX
CX
+ VX 
CBYPASS
Figure 1. Lossless Inductor Sensing
Since the inductance tolerances are normally observed
to be 20%, the resistor, RX, has to be tuned on board by
examining the transient voltage. If the output voltage
transient has an initial dip below the minimum load line
requirement with a slow recovery, RX is chosen too small.
Vice versa, with a resistance too large, the output voltage
transient has only a small initial dip and the recovery is
too fast, thus causing a ringback.
Using current sense resistor in series with the inductor
can have better accuracy, but the efficiency is a tradeoff.
Considering the equivalent inductance (LESL) of the current
sense resistor, an RC filter is recommended. The RC filter
calculation method is similar to the abovementioned
inductor DCR sensing method .
Loop Control
The RT8856 adopts Richtek's proprietary NAVPTM topology.
NAVPTM is based on the finitegain peak current mode
PWM topology. The output voltage, VOUT, will decrease
with increasing output load current. The control loop
consists of PWM modulator with power stage, current
sense amplifier and error amplifier as shown in Figure 2.
RT8856
Clock
S
PWM
Logic
R
UGATEx
LGATEx
CMP
COMP2
ISENx
+
VCS
AI ISENx_N

VOFS
EA
+
VDAC
COMP
FB
SOFT
RGND
VIN
HS_FET
L
RX CX
LS_FET
VOUT
RC
C
C2 C1
R2
R1
VCC_SENSE
CSOFT
VSS_SENSE
Figure 2. Simplified Schematic for Droop and Remote
Sense in CCM
www.richtek.com
16
Similar to the peak current mode control with finite
compensator gain, the HS_FET ontime is determined by
both the internal clock and the PWM comparator which
compares the EA output with the output of current sense
amplifier. When load current increases, VCS increases,
the steady state COMP voltage also increases and makes
the VOUT decrease, hence achieving AVP. A nearDC offset
(VOFS) is added to the output EA to cancel the inherent
output offset of finitegain peak current mode controller.
In RFM, HS_FET is turned on with constant TON when
VCS is lower than VCOMP2. Once the HS_FET is turned off,
LS_FET is turned on automatically. By RingingFree
Technique, the LS_FET allows only partial of negative
current when the inductor freewheeling current reaches
negative. The switching frequency will be proportionately
reduced, thus the conduction and switching losses will
be greatly reduced.
Droop Setting (with Temperature Compensation)
It's very easy to achieve Active Voltage Positioning (AVP)
by properly setting the error amplifier gain with respect to
the native droop characteristics. The target is to have
Equation (3)
VOUT = VSOFT − ILOAD x RDROOP
(3)
then solving the switching condition VCOMP2 = VCS in
Figure 2 yields the desired error amplifier gain as
AV
=
R2
R1
=
AI × RSENSE
RDROOP
(4)
where AI is the internal current sense amplifier gain. RSENSE
is the current sense resistor. If there is no external sense
resistor, it is the DCR of the inductor. RDROOP is the
resistive slope value of the converter output and is the
desired static output impedance, e.g. −1.9mΩ or −3mΩ
for IMVP6.5 specification. Increasing AV can make load
line more shallow as shown in Figure 3.
VOUT
AV2 > AV1
AV2
AV1
0
Load Current
Figure 3. Error Amplifier Gain (AV) Influence on VOUT
Accuracy
DS885603 June 2011