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MTV212MN64 View Datasheet(PDF) - Myson Century Inc

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MTV212MN64
Myson
Myson Century Inc Myson
MTV212MN64 Datasheet PDF : 27 Pages
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MYSON
TECHNOLOGY
MTV212M64
(Rev. 1.2)
= 4 Select AUXRAM bank 4.
= 5 Select AUXRAM bank 5.
4. Extra I/O
The extra I/O is a group of I/O pins located in XFR area. Port4 is output mode only. Port5 can be used as
both output and input, because Port5's pin is open drain type, user must write Port5's corresponding bit to
"1" in input mode.
Reg name addr
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
PORT4 38h (w)
P42
P41
P40
PORT5 39h (r/w)
P56
P55
P54
P53
P52
P51
P50
PORT4 (w) : Port 4 data output value.
PORT5 (r/w) : Port 5 data input/output value.
5. PWM DAC
Each PWM DAC converter's output pulse width is controlled by an 8-bit register in XFR. The frequency of
PWM clk is 47KHz or 94KHz, selected by PWMF. And the total duty cycle step of these DAC outputs is 253
or 256, selected by DIV253. If DIV253=1, writing FDH/FEH/FFH to DAC register generates stable high
output. If DIV253=0, the output will pulse low at least once even if the DAC register's content is FFH. Writing
00H to DAC register generates stable low output.
Reg name addr
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
DA0
20h (r/w)
Pulse width of PWM DAC 0
DA1
21h (r/w)
Pulse width of PWM DAC 1
DA2
22h (r/w)
Pulse width of PWM DAC 2
DA3
23h (r/w)
Pulse width of PWM DAC 3
DA4
24h (r/w)
Pulse width of PWM DAC 4
DA5
25h (r/w)
Pulse width of PWM DAC 5
DA6
26h (r/w)
Pulse width of PWM DAC 6
DA7
27h (r/w)
Pulse width of PWM DAC 7
DA8
28h (r/w)
Pulse width of PWM DAC 8
DA9
29h (r/w)
Pulse width of PWM DAC 9
DA10 2Ah (r/w)
Pulse width of PWM DAC 10
DA11 2Bh (r/w)
Pulse width of PWM DAC 11
DA12 2Ch (r/w)
Pulse width of PWM DAC 12
DA13 2Dh (r/w)
Pulse width of PWM DAC 13
DA0-13 (r/w) : The output pulse width control for DA0-13.
* All of PWM DAC converters are centered with value 80h after power on.
6. H/V SYNC Processing
The H/V SYNC processing block performs the functions of composite signal separation/insertion, SYNC
inputs presence check, frequency counting, polarity detection and control, as well as the protection of
VBLANK output while VSYNC speed up in high DDC communication clock rate. The present and frequency
function block treat any pulse shorter than one OSC period as noise.
Revision 1.2
- 8-
2000/07/04
 

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