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MTV212MV64U View Datasheet(PDF) - Myson Century Inc

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MTV212MV64U
Myson
Myson Century Inc Myson
MTV212MV64U Datasheet PDF : 27 Pages
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MYSON
TECHNOLOGY
MTV212M64
(Rev. 1.2)
reset. S/W must write this register a valid value after the USB enumeration process.
10.2 Endpoint 0 receive
After receiving a packet and placing the data into the Endpoint 0 receive FIFO (RC0FIFO), MTV212M
updates the Endpoint 0 status register (EP0STUS) to record the receive status and then generates an
Endpoint 0 receive interrupt (RC0I). S/W can read the EP0STUS register for the recent transfer information,
which includes the data byte count (RC0cnt), data direction (EP0dir), SETUP token flag (EP0set) and data
valid flag (RC0err). The received data is always stored into RC0FIFO and the RC0cnt is always updated for
DATA packets following SETUP tokens. The data following an OUT token is written into the RC0FIFO, and
the RC0cnt is updated unless Endpoint 0 STALL (EP0stall) or Endpoint 0 receive NAK (RC0nak) is set. The
RC0I interrupt will happen in case where the RC0cnt/RC0FIFO is updated.
10.3 Endpoint 0 transmit
After detecting a valid Endpoint 0 IN token, MTV212M automatically transmit the data pre-stored in the
Endpoint 0 transmit FIFO (TX0FIFO) to the USB bus if the Endpoint 0 transmit ready flag (TX0rdy) is set and
the EP0stall is cleared. The number of byte to be transmitted is base on the Endpoint 0 transmit byte count
register (TX0cnt). The DATA0/1 token to be transmitted is base on the Endpoint 0 transmit toggle control bit
(TX0tgl). After the TX0FIFO is updated, TX0rdy should be set to 1. This enables the MTV212M to respond to
an Endpoint 0 IN packet. TX0rdy is cleared and an Endpoint 0 transmit interrupt (TX0I) is generated once the
USB host acknowledges the data transmission. The interrupt service routine can check TX0rdy to confirm
that the data transfer was successful.
10.4 Endpoint 1 transmit
Endpoint 1 is capable of transmit only. This endpoint is enable when the Endpoint1 configured control bit
(EP1Cfgd) is set. After detecting a valid Endpoint 1 IN token, MTV212M automatically transmit the data pre-
stored in the Endpoint 1 transmit FIFO (TX1FIFO) to the USB bus if the Endpoint 1 transmit ready flag
(TX1rdy) is set and the EP1stall is cleared. The number of byte to be transmitted is base on the Endpoint 1
transmit byte count register (TX1cnt). The DATA0/1 token to be transmitted is base on the Endpoint 1
transmit toggle control bit (TX1tgl). After the TX1FIFO is updated, TX1rdy should be set to 1. This enables
the MTV212M to respond to an Endpoint 1 IN packet. TX1rdy is cleared and an Endpoint 1 transmit interrupt
(TX1I) is generated once the USB host acknowledges the data transmission. The interrupt service routine
can check TX0rdy to confirm that the data transfer was successful.
10.5 USB Control and Status
Other USB control bits include the USB enable (ENUSB), SUSPEND (Susp), RESUME (RsmO), Control
Read (CtrRD), and corresponding interrupt enable bits. The CtrRD should be set when program detects the
current transfer is an Endpoint0 Control Read Transfer. Once this bit is set, the MTV212M will stall an
Endpoint0 OUT packet with DATA toggle 0 or byte count other than 0. Other USB status flag includes the
USB reset interrupt (USBrstI), RESUME interrupt (RsmI), and USB bus active flag (USBactv). The USBactv
flag is set once the MTV212M detect the USB bus activity. S/W should read and clear it every 3 ms to
identify the suspend condition. Writing a "1" to the USBactv flag will not change its value.
10.6 Suspend and Resume
Once the Suspend condition is asserted, S/W can set the Susp bit to stop the USBSIE's clock. In the mean
time, the 3.3V Regulator is operating in low power mode. S/W can further save the device power by force the
8051 CPU core into the Power Down or Idle mode by setting the PCON register in SFR area. In the Idel
mode, the X'tal keeps oscillating and CPU can be waken-up by the trigger of any enabled interrupt. In the
Power Down mode, the X'tal is stop, but CPU can be waken-up by the trigger of enabled INT1's source. In
short, S/W can keep the RsmI alive before enter the suspend mode.
Reg name addr
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
USBADR 60h (r/w) ENUSB
USBadr
INTFLG 61h (r/w) USBrstI RC0I TX1I TX0I RsmI
INTEN 62h (w) EUrstI ERC0I ETX1I ETX0I ERsmI
EP0STUS 63h (r) RC0tgl RC0err EP0dir EP0set
RC0cnt
Revision 1.2
- 19 -
2000/07/04
 

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