MTV212MV64 View Datasheet(PDF) - Myson Century Inc

Part Name

Description

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MTV212MV64

8051 Embedded Monitor Controller MTP Type

Myson Century Inc 

MYSON

TECHNOLOGY

MTV212M64

(Rev. 1.2)

* Please see the attachments about "Master IIC Receive Timing".

Reg name

IICCTR

IICSTUS

IICSTUS

INTFLG

INTFLG

INTEN

MBUF

RCABUF

TXABUF

SLVAADR

RCBBUF

TXBBUF

SL VB ADR

DBUF

addr

00h (r/w)

01h (r)

02h (r)

03h (r)

03h (w)

04h (w)

05h (r/w)

06h (r)

06h (w)

07h (w)

08h (r)

08h (w)

09h (w)

0Ah (w)

bit7

DDC2

WadrB

MAckIn

TXBI

ETXBI

ENSlvA

ENSlvB

bit6

WadrA

Hifreq

RCBI

ERCBI

bit5

bit4

bit3

bit2

bit1

bit0

MAckO P

S

SlvRWB SAckIn SLVS

SlvAlsb1 SlvAlsb0

Hbusy

SlvBMI TXAI RCAI SlvAMI DbufI MbufI

SlvBMI

SlvAMI

MbufI

ESlvBMI ETXAI ERCAI ESlvAMI EDbufI EMbufI

Master IIC receive/transmit data buffer

Slave A IIC receive buffer

Slave A IIC transmit buffer

Slave A IIC address

Slave B IIC receive buffer

Slave B IIC transmit buffer

Slave B IIC address

DDC1 transmit data buffer

IICCTR (r/w) : IIC interface control register.

DDC2 = 1 → MTV212M is in DDC2 mode, write "0" can clear it.

= 0 → MTV212M is in DDC1 mode.

MAckO = 1 → In master receive mode, NACK is returned by MTV212M.

= 0 → In master receive mode, ACK is returned by MTV212M.

S, P = ↑, 0 → Start condition when Master IIC is not during transfer.

= X, ↑ → Stop condition when Master IIC is not during transfer.

= 1, X → Will resume transfer after a read/write MBUF operation.

= X, 0 → Force HSCL low and occupy the master IIC bus.

* A write/read MBUF operation can be recognized only after 10us of the MbufI flag's rising edge.

IICSTUS (r) : IIC interface status register.

WadrB = 1 → The data in RCBBUF is word address.

WadrA = 1 → The data in RCABUF is word address.

SlvRWB = 1 → Current transfer is slave transmit

= 0 → Current transfer is slave receive

SAckIn = 1 → The external IIC host respond NACK.

SLVS = 1 → The slave block has detected a START, cleared when STOP detected.

SlvAlsb1,SlvAlsb0 : The 2 LSB which host send to Slave A block.

MAckIn = 1 → Master IIC bus error, no ACK received from the slave IIC device.

= 0 → ACK received from the slave IIC device.

Hifreq = 1 → MTV212M has detected a higher than 200Hz clock on the VSYNC pin.

Hbusy = 1

→ Host drives the HSCL pin to low.

INTFLG (w) : Interrupt flag. A interrupt event will set its individual flag, and, if the corresponding interrupt

enable bit is set, the 8051 INT1 source will be driven by a zero level. Software MUST clear

this register while serve the interrupt routine.

SlvBMI = 1 → No action.

= 0 → Clear SlvBMI flag.

SlvAMI = 1 → No action.

= 0 → Clear SlvAMI flag.

MbufI = 1 → No action.

= 0 → Clear Master IIC bus interrupt flag (MbufI).

INTFLG (r) : Interrupt flag.

Revision 1.2

- 16 -

2000/07/04

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