MTV212MS64 View Datasheet(PDF) - Myson Century Inc
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MTV212MS64 Datasheet PDF : 27 Pages
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MYSON
TECHNOLOGY
MTV212M64
(Rev. 1.2)
lock in DDC2B mode if a valid IIC address (1010xxxb) has been detected on HSCL/HSDA bus. The DDC2
flag reflects the current DDC status, S/W may clear it by writing a "0" to it.
7.3 Slave Mode IIC function Block
The slave mode IIC block is connected to HSDA and HSCL pins. This block can receive/transmit data using
IIC protocol. There are 2 slave addresses MTV212M can respond to. S/W may write the
SLVAADR/SLVBADR register to determine the slave addresses. The SlaveA address can be configured to
5-bits, 6-bits or 7-bits by S/W setting the SlvAbs1 and SlvAbs0 control bits.
In receive mode, the block first detects IIC slave address match condition then issues a SlvAMI/SlvBMI
interrupt. If the matched address is slave A, MTV212M will save the matched address's 2 LSB bits to
SlvAlsb1 and SlvAlsb0 register. The data from HSDA is shifted into shift register then written to
RCABUF/RCBBUF register when a data byte is received. The first byte loaded is word address (slave
address is dropped). This block also generates a RCAI/RCBI (receive buffer full interrupt) every time when
the RCABUF/RCBBUF is loaded. If S/W can't read out the RCABUF/RCBBUF in time, the next byte in shift
register will not be written to RCABUF/RCBBUF and the slave block return NACK to the master. This feature
guarantees the data integrity of communication. The WadrA/WadrB flag can tell S/W that if the data in
RCABUF/RCBBUF is a word address.
In transmit mode, the block first detects IIC slave address match condition then issues a SlvAMI/SlvBMI
interrupt. In the mean time, the SlvAlsb1/SlvAlsb0 is also updated if the matched address is slave A, and the
data pre-stored in the TXABUF/TXBBUF is loaded into shift register, result in TXABUF/TXBBUF empty and
generates a TXAI/TXBI (transmit buffer empty interrupt). S/W should write the TXABUF/TXBBUF a new byte
for next transfer before shift register empty. Fail to do this will cause data corrupt. The TXAI/TXBI occurs
every time when shift register reads out the data from TXABUF/TXBBUF.
The SlvAMI/SlvBMI is cleared by writing "0" to corresponding bit in INTFLG register. The RCAI/RCBI is
cleared by reading RCABUF/RCBBUF. The TXAI/TXBI is cleared by writing TXABUF/TXBBUF. If the control
bit ENSCL is set, the block will hold HSCL low until the RCAI/RCBI/TXAI/TXBI is cleared.
*Please see the attachments about "Slave IIC Block Timing".
7.4 Master Mode IIC Function Block
The master mode IIC block can be connected to the ISDA /ISCL pins or the HSDA/HSCL pins, select by
Msel control bit. Its speed can be selected to 50KHz-400KHz by S/W setting the MIICF1/MIICF0 control bit.
The software program can access the external IIC device through this interface. Since the EDID/VDIF data
and the display information share the common EEPROM, precaution must be taken to avoid bus conflicting
while Msel=0. In DDC1 mode or IICpass=0, the ISCL/ISDA is controlled by MTV212M only. In DDC2 mode
and IICpass flag is set, the host may access the EEPROM directly. Software can test the HSCL condition by
reading the Hbusy flag, which is set in case of HSCL=0, and keeps high for 100uS after the HSCL's rising
edge. S/W can launch the master IIC transmit/receive by clearing the P bit. Once P=0, MTV212M will hold
HSCL low to isolate the host's access to EEPROM. A summary of master IIC access is illustrated as follows.
7.4.1. To write IIC Device
1. Write MBUF the Slave Address.
2. Set S bit to Start.
3. After the MTV212M transmit this byte, a MbufI interrupt will be triggered.
4. Program can write MBUF to transfer next byte or set P bit to stop.
* Please see the attachments about "Master IIC Transmit Timing".
7.4.2. To read IIC Device
1. Write MBUF the Slave Address.
2. Set S bit to Start.
3. After the MTV212M transmit this byte, a MbufI interrupt will be triggered.
4. Set or reset the MAckO flag according to the IIC protocol.
5. Read out MBUF the useless byte to continue the data transfer.
6. After the MTV212M receives a new byte, the MbufI interrupt is triggered again.
7. Read MBUF also trigger the next receive operation, but set P bit before read can terminate the operation.
Revision 1.2
- 15 -
2000/07/04
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