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MTV212MS64 View Datasheet(PDF) - Myson Century Inc

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MTV212MS64
Myson
Myson Century Inc Myson
MTV212MS64 Datasheet PDF : 27 Pages
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MYSON
TECHNOLOGY
MTV212M64
(Rev. 1.2)
HPRchg= 1
=0
VPRchg= 1
=0
HPLchg= 1
=0
VPLchg = 1
=0
HFchg = 1
=0
VFchg = 1
=0
Vsync = 1
=0
No action.
Clear HSYNC presence change flag.
No action.
Clear VSYNC presence change flag.
No action.
Clear HSYNC polarity change flag.
No action.
Clear VSYNC polarity change flag.
No action.
Clear HSYNC frequency change flag.
No action.
Clear VSYNC frequency change flag.
No action.
Clear VSYNC interrupt flag.
INTFLG (r) : Interrupt flag.
HPRchg= 1 Indicates a HSYNC presence change.
VPRchg= 1 Indicates a VSYNC presence change.
HPLchg= 1 Indicates a HSYNC polarity change.
VPLchg = 1 Indicates a VSYNC polarity change.
HFchg = 1 Indicates a HSYNC frequency change or counter overflow.
VFchg = 1 Indicates a VSYNC frequency change or counter overflow.
Vsync = 1 Indicates a VSYNC interrupt.
INTEN (w) : Interrupt enable.
EHPR = 1 Enable HSYNC presence change interrupt.
EVPR = 1 Enable VSYNC presence change interrupt.
EHPL = 1 Enable HSYNC polarity change interrupt.
EVPL = 1 Enable VSYNC polarity change interrupt.
EHF = 1 Enable HSYNC frequency change / counter overflow interrupt.
EVF = 1 Enable VSYNC frequency change / counter overflow interrupt.
EVsync = 1 Enable VSYNC interrupt.
7. DDC & IIC Interface
7.1 DDC1 Mode
The MTV212M enters DDC1 mode after Reset. In this mode, VSYNC is used as data clock. The HSCL pin
should remain at high. The data output to the HSDA pin is taken from a shift register in MTV212M. The shift
register fetch data byte from the DDC1 data buffer (DBUF) then send it in 9 bits packet formats which
includes a null bit (=1) as packet separator. The DBUF set the DbufI interrupt flag when the shift register
read out the data byte from DBUF. Software needs to write EDID data to DBUF as soon as the DbufI is set.
The DbufI interrupt is automatically cleared when Software writes a new data byte to DBUF. The DbufI
interrupt can be mask or enable by EDbufI control bit.
7.2 DDC2B Mode
The MTV212M switches to DDC2B mode when it detects a high to low transition on the HSCL pin. Once
MTV212M enters DDC2B mode, S/W can set IICpass control bit to allow HOST access EEPROM directly.
Under such condition, the HSDA and HSCL are directly bypassed to ISDA and ISCL pins. The other way to
perform DDC2 function is to clear IICpass and config the Slave A IIC block to act as EEPROM behavior. The
Slave A block's slave address can be chosen by S/W as 5-bits, 6-bits or 7-bits. For example, if S/W choose
5-bits slave address as 10100b, the slave IIC block A will respond to slave address 10100xxb and save the 2
LSB "xx" in XFR. This feature enables MTV212M to meet PC99 requirement.
The MTV212M will return to DDC1 mode if HSCL is kept high for 128 VSYNC clock period. However, it will
Revision 1.2
- 14 -
2000/07/04
 

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