MYSON
TECHNOLOGY
MTV212M64
(Rev. 1.2)
= 0 → HSYNC input's off level is low.
Voff* = 1 → VSYNC input's off level is high.
= 0 → VSYNC input's off level is low.
*Hoff and Voff are valid when Hpre=0 or Vpre=0.
HCNTH (r) : H-Freq counter's high bits.
Hovf = 1 → H-Freq counter is overflow, this bit is clear by H/W when condition removed.
HF13 - HF8 : 6 high bits of H-Freq counter.
HCNTL (r) : H-Freq counter's low byte.
VCNTH (r) : V-Freq counter's high bits.
Vovf = 1 → V-Freq counter is overflow, this bit is clear by H/W when condition removed.
VF11 - 8 :
4 high bits of V-Freq counter.
VCNTL (r) : V-Freq counter's low byte.
HVCTR0 (w) : H/V SYNC processor control register 0.
C1, C0 = 1,1 → Select CVSYNC as the polarity, freq and VBLANK source.
= 1,0 → Select VSYNC as the polarity, freq and VBLANK source.
= 0,0 → Disable composite function.
= 0,1 → H/W auto switch to CVSYNC when CVpre=1 and VSpre=0.
NoHins = 1 → HBLANK has no insert pulse in composite mode.
= 0 → HBLANK has insert pulse in composite mode.
HBpl = 1 → negative polarity HBLANK output.
= 0 → positive polarity HBLANK output.
VBpl = 1 → negative polarity VBLANK output.
= 0 → positive polarity VBLANK output.
HVCTR2 (w) : Self-test pattern generator control.
Selft = 1 → enable generator.
= 0 → disable generator.
STF1,STF0 = 1,1 → 63.5KHz(horizontal) output selected.
= 1,0 → 47.6KHz(horizontal) output selected.
= 0,0 → 31.75KHz(horizontal) output selected.
Rt1, Rt0= 0,0 → positive cross-hatch pattern output.
= 0,1 → negative cross-hatch pattern output.
= 1,0 → full white pattern output.
= 1,1 → full black pattern output.
STE = 1 → enable STOUT output.
= 0 → disable STOUT output.
HVCTR3 (w) : HSYNC clamp pulse control register.
CLPEG = 1 → Clamp pulse follows HSYNC leading edge.
= 0 → Clamp pulse follows HSYNC trailing edge.
CLPPO = 1 → Positive polarity clamp pulse output.
= 0 → Negative polarity clamp pulse output.
CLPW2 : CLPW0 : Pulse width of clamp pulse is
[(CLPW2:CLPW0) + 1] x 0.167 µs for 12MHz X’tal selection.
INTFLG (w) : Interrupt flag. An interrupt event will set its individual flag, and, if the corresponding interrupt
enable bit is set, the 8051 core's INT1 source will be driven by a zero level. Software MUST
clear this register while serve the interrupt routine.
Revision 1.2
- 13 -
2000/07/04