MTV212MS64 View Datasheet(PDF) - Myson Century Inc
Part Name
Description
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MTV212MS64 Datasheet PDF : 27 Pages
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MYSON
TECHNOLOGY
MTV212M64
(Rev. 1.2)
Hor. Total time (A)
Hor. Active time (D)
Hor. F. P. (E)
SYNC pulse width (B)
Hor. B. P. (C)
MTV212M Self-Test pattern timing
63.5KHz, 60Hz
47.6KHz, 60Hz
Absolute time H dots Absolute time H dots
15.75us
1280
21.0us
1024
12.05us
979.3
16.07us
783.2
0.2us
16.25
0.28us
12
1.5us
122
2us
90
2us
162.54
2.67us
110
31.7KHz, 60Hz
Absolute time H dots
31.5us
640
24.05us
488.6
0.45us
9
3us
61
4us
81.27
Vert. Total time (O)
Vert. Active time (R)
Vert. F. P. (S)
SYNC pulse width (P)
Vert. B. P. (Q)
Absolute time
16.663ms
15.655ms
0.063ms
0.063ms
0.882ms
V lines
1024
962
3.87
3.87
54.2
Absolute time
16.663ms
15.655ms
0.063ms
0.063ms
0.882ms
V lines
768
721.5
2.9
2.9
40.5
Absolute time
16.663ms
15.655ms
0.063ms
0.063ms
0.882ms
V lines
480
451
1.82
1.82
25.4
* 8 x 8 blocks of cross hatch pattern in display region.
6.7 HSYNC Clamp Pulse Output
The HCLAMP output is active by setting “HCLPE” control bit. The HCLAMP’s leading edge position, pulse
width and polarity is S/W controllable.
6.8 VSYNC Interrupt
The MTV212M check the VSYNC input pulse and generate an interrupt at its leading edge. The VSYNC flag
is set each time when MTV212M detects a VSYNC pulse. The flag is cleared by S/W writing a "0".
6.9 H/V SYNC Processor Register
Reg name
HVSTUS
HCNTH
HCNTL
VCNTH
VCNTL
HVCTR0
HVCTR2
HVCTR3
INTFLG
INTEN
addr
40h (r)
41h (r)
42h (r)
43h (r)
44h (r)
40h (w)
42h (w)
43h (w)
48h (r/w)
49h (w)
bit7
bit6
bit5
CVpre
Hpol
Hovf
HF13
HF7 HF6 HF5
Vovf
VF7
VF6
VF5
C1
C0 NoHins
Selft
CLPEG CLPPO
HPRchg VPRchg HPLchg
EHPR EVPR EHPL
bit4
Vpol
HF12
HF4
VF4
STF1
CLPW2
VPLchg
EVPL
bit3
Hpre
HF11
HF3
VF11
VF3
STF0
CLPW1
HFchg
EHF
bit2
Vpre
HF10
HF2
VF10
VF2
Rt1
CLPW0
VFchg
EVF
bit1
Hoff
HF9
HF1
VF9
VF1
HBpl
Rt0
bit0
Voff
HF8
HF0
VF8
VF0
VBpl
STE
Vsync
EVsync
HVSTUS (r) : The status of polarity, present and static level for HSYNC and VSYNC.
CVpre = 1 → The extracted CVSYNC is present.
= 0 → The extracted CVSYNC is not present.
Hpol = 1 → HSYNC input is positive polarity.
= 0 → HSYNC input is negative polarity.
Vpol = 1 → VSYNC (CVSYNC) is positive polarity.
= 0 → VSYNC (CVSYNC) is negative polarity.
Hpre = 1 → HSYNC input is present.
= 0 → HSYNC input is not present.
Vpre = 1 → VSYNC input is present.
= 0 → VSYNC input is not present.
Hoff* = 1 → HSYNC input's off level is high.
Revision 1.2
- 12 -
2000/07/04
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