MTV312M64 View Datasheet(PDF) - Myson Century Inc

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MTV312M64

8051 Embedded Monitor Controller Flash Type with ISP

Myson Century Inc 

MYSON

TECHNOLOGY

MTV312M64

(Rev 0.99)

the IIC Master by setting/clearing the EN128w/En256w bit. Besides, if the Only128 control bit is set, the

SlaveA only accesses the lower 128 bytes of the DDCRAM.

The MTV312M returns to DDC1 mode if HSCL is kept high for 128 VSYNC clock period. However, it locks in

DDC2B mode if a valid IIC address (1010xxxb) has been detected on HSCL/HSDA bus. The DDC2 flag

reflects the current DDC status, S/W may clear it by writing a "0" to it.

7.2 SlaveB Block

The SlaveB IIC block is connected to HSDA and HSCL pins. This block can receive/transmit data using IIC

protocols. S/W may write the SLVBADR register to determine the slave addresses.

In receive mode, the block first detects IIC slave address matching the condition then issues a SlvBMI

interrupt. The data from HSDA is shifted into shift register then written to RCBBUF register when a data byte

is received. The first byte loaded is word address (slave address is dropped). This block also generates a

RCBI (receives buffer full interrupt) every time when the RCBBUF is loaded. If S/W is not able to read out

the RCBBUF in time, the next byte in shift register is not written to RCBBUF and the slave block returns

NACK to the master. This feature guarantees the data integrity of communication. The WadrB flag can tell

S/W whether the data in RCBBUF is a word address or not.

In transmit mode, the block first detects IIC slave address matching the condition, then issues a SlvBMI

interrupt. In the meantime, the data pre-stored in the TXBBUF is loaded into shift register, resulting in

TXBBUF emptying and generates a TXBI (transmit buffer empty interrupt). S/W should write the TXBBUF a

new byte for the next transfer before shift register empties. A failure of this process causes data corrupt.

The TXBI occurs every time when shift register reads out the data from TXBBUF.

The SlvBMI is cleared by writing "0" to corresponding bit in INTFLG register. The RCBI is cleared by reading

out RCBBUF. The TXBI is cleared by writing TXBBUF.

*Please refer to the attachments about "Slave IIC Block Timing".

7.3 Master Mode IIC Function Block

The master mode IIC block can be connected to the ISDA /ISCL pins or the HSDA/HSCL pins, selected by

Msel control bit. Its speed can be selected within the range of 50KHz-400KHz by S/W setting the

MIICF1/MIICF0 control bit. The software program can access the external IIC device through this interface.

A summary of master IIC access is illustrated as follows.

7.3.1. To write IIC Device

1. Write MBUF the Slave Address.

2. Set S bit to Start.

3. After the MTV312M transmits this byte, a MbufI interrupt is triggered.

4. Programs can write MBUF to transfer next byte or set P bit to stop.

* Please refer to the attachments about "Master IIC Transmit Timing".

7.3.2. To read IIC Device

1. Write MBUF the Slave Address.

2. Set S bit to Start.

3. After the MTV312M transmits this byte, a MbufI interrupt is triggered.

4. Set or reset the MAckO flag according to the IIC protocol.

5. Read out MBUF the useless byte to continue the data transfer.

6. After the MTV312M receives a new byte, the MbufI interrupt is triggered again.

7. Read MBUF also trigger the next receive operation, but set P bit before read can terminate the operation.

* Please refer to the attachments about "Master IIC Receive Timing".

Reg name addr

bit7

bit6

bit5

bit4

bit3

bit2

bit1

bit0

IICCTR F00h (r/w) DDC2

MAckO P

S

IICSTUS F01h (r) WadrB

SlvRWB SAckIn SLVS

MAckIn

INTFLG F03h (r) TXBI RCBI SlvBMI STOPI ReStaI WSlvAI

MbufI

INTFLG F03h (w)

SlvBMI STOPI ReStaI WSlvAI

MbufI

Revision 0.99

- 16 -

2001/07/26

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