MTV230MS64 View Datasheet(PDF) - Myson Century Inc
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MTV230MS64 Datasheet PDF : 31 Pages
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MYSON
TECHNOLOGY
MTV230M
(Rev 1.0)
shown in the table below. The programmable vertical size ranges are 270 lines to maximum 2130 lines.
The vertical display center for full screen display could be figured out according to the information of vertical
starting position register (VERTD) and OSDVS input. The vertical display starting position from the leading
edge of OSDVS is calculated using the following equation:
Vertical delay time = (VERTD * 4 +1) * H
, where H = one horizontal line display time
Repeat Line Weight of Character
CH6 – CH0
CH6, CH5 = 11
CH6, CH5 = 10
CH6, CH5 = 0x
CH4 = 1
CH3 = 1
CH2 = 1
CH1 = 1
CH0 = 1
Repeat Line Weight
+18*3
+18*2
+18
+16
+8
+4
+2
+1
Repeat Line Number of character
Repeat Line
Repeat Line #
Weight 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
+1
- - - - - - - -v- - - - - - - - -
+2
- - - -v- - - - - - -v- - - - -
+4
- -v- - -v- - -v- - -v- - -
+8
-v-v-v-v-v-v-v-v- -
+16
- vvvvvvvvvvvvvvvv -
+17
vvvvvvvvvvvvvvvvv -
+18
vvvvvvvvvvvvvvvvvv
Note: “v” means the nth line in the character would be repeated once, while “-“ means the nth line in the
character would not be repeated.
11.3 Display RAM
The display RAM contains character address, attribute and row control registers. The display registers have
450 locations which are allocated between (row 0, column 0) to (row14, column 29). Each display register
has its corresponding character address on ADDRESS bytes, and its corresponding color, blink bit,
background color on ATTRIBUTE bytes. The row control register is allocated at column 30 from row 0 to row
14 of address bytes. It is used to set character size to each respective row. If double width character is
chosen, only even column characters could be displayed on screen and the odd column characters will be
hidden.
There are 4 registers to program display RAM: OSDRA, OSDCA, OSDDT0 and OSDDT1. OSDRA is the row
address; OSDCA is the column address; OSDDT0 and OSDDT1 are the programming data byte. The 2 MSB
(bit 7 - bit 6) of OSDRA register are used to distinguish ADDRESS byte when they are set to “0, 0” and
ATTRIBUTE byte when they are set to “0, 1”. OSDDT0 and OSDDT1 are used to differentiate the MSB (bit 8)
of display characters address. The MSB (bit 8) of display characters address will be equal to ”0“ while data
byte is filled into OSDDT0, or “1” while data byte is filled into OSDDT1; and OSDDT0 or OSDDT1 are the 8
LSB (bit 7 - bit 0) of display characters address.
The programming row (OSDRA) and column (OSDCA) address of display RAM will be incremented
automatically when MCU continues to update OSDDT0 or OSDDT1. It is used to save the program ROM
size of MCU while massive data update or full screen data change.
Since bit 8 is fixed on OSDDT0 (OSDDT1) while programming ADDRESS byte, the continued OSDDT0
(OSDDT1) will be the same bank of lower 256 fonts (upper 256 fonts) until program another data byte
OSDDT1 (OSDDT0) register.
Revision 1.0
- 19 -
2000/11/15
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