MYSON
TECHNOLOGY
MTV230M
(Rev 1.0)
Reg name
IICCTR
IICSTUS
IICSTUS
INTFLG
INTFLG
INTEN
MBUF
RCABUF
TXABUF
SLVAADR
RCBBUF
TXBBUF
SL VB ADR
addr
bit7
F00h (r/w)
F01h (r) WadrB
F02h (r) MAckIn
F03h (r) TXBI
F03h (w)
F04h (w) ETXBI
F05h (r/w)
F06h (r)
F06h (w)
F07h (w) ENSlvA
F08h (r)
F08h (w)
F09h (w) ENSlvB
bit6
bit5
bit4
WadrA SlvRWB SAckIn
bit3
SLVS
bit2
bit1
bit0
MAckO P
S
SlvAlsb1 SlvAlsb0
RCBI
ERCBI
SlvBMI TXAI RCAI SlvAMI
SlvBMI
SlvAMI
ESlvBMI ETXAI ERCAI ESlvAMI
Master IIC receive/transmit data buffer
Slave A IIC receive buffer
Slave A IIC transmit buffer
Slave A IIC address
Slave B IIC receive buffer
Slave B IIC transmit buffer
Slave B IIC address
MbufI
MbufI
EMbufI
IICCTR (r/w) : IIC interface control register.
MAckO = 1 → In master receive mode, NACK is returned by MTV230M.
= 0 → In master receive mode, ACK is returned by MTV230M.
S, P = ↑, 0 → Start condition when Master IIC is not during transfer.
= X, ↑ → Stop condition when Master IIC is not during transfer.
= 1, X → Will resume transfer after a read/write MBUF operation.
IICSTUS (r) : IIC interface status register.
WadrB = 1 → The data in RCBBUF is word address.
WadrA = 1 → The data in RCABUF is word address.
SlvRWB = 1 → Current transfer is slave transmit.
= 0 → Current transfer is slave receive.
SAckIn = 1 → The external IIC host respond NACK.
SLVS = 1 → The slave block has detected a START, cleared when STOP detected.
SlvAlsb1,SlvAlsb0 : The 2 LSB which host send to Slave A block.
MAckIn = 1 → Master IIC bus error, no ACK received from the slave IIC device.
= 0 → ACK received from the slave IIC device.
INTFLG (w) : Interrupt flag. A interrupt event will set its individual flag, and, if the corresponding interrupt
enable bit is set, the 8051 INT1 source will be driven by a zero level. Software MUST clear
this register while serve the interrupt routine.
SlvBMI = 1 → No action.
= 0 → Clears SlvBMI flag.
SlvAMI = 1 → No action.
= 0 → Clears SlvAMI flag.
MbufI = 1 → No action.
= 0 → Clears Master IIC bus interrupt flag (MbufI).
INTFLG (r) : Interrupt flag.
TXBI = 1 → Indicates the TXBBUF needs a new data byte, cleared by writing TXBBUF.
RCBI = 1 → Indicates the RCBBUF has received a new data byte, cleared by reading
RCBBUF.
SlvBMI = 1 → Indicates the slave IIC address B matches condition.
TXAI = 1 → Indicates the TXABUF needs a new data byte, cleared by writing TXABUF.
RCAI = 1 → Indicates the RCABUF has received a new data byte, cleared by reading
RCABUF.
SlvAMI = 1 → Indicates the slave IIC address A match condition.
Revision 1.0
- 14 -
2000/11/15