MTV230MS64 View Datasheet(PDF) - Myson Century Inc

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MTV230MS64

8051 Embedded LCD Monitor Controller with Flash OSD

Myson Century Inc 

MYSON

TECHNOLOGY

MTV230M

(Rev 1.0)

= 0 → Positive polarity VBLANK output.

HVCTR3 (w) : HSYNC clamp pulse control register.

CLPEG = 1 → Clamp pulse follows HSYNC leading edge.

= 0 → Clamp pulse follows HSYNC trailing edge.

CLPPO = 1 → Positive polarity clamp pulse output.

= 0 → Negative polarity clamp pulse output.

CLPW2 : CLPW0 : Pulse width of clamp pulse is

[(CLPW2:CLPW0) + 1] x 0.167 µs for 12MHz X’tal selection.

INTFLG (w) : Interrupt flag. An interrupt event will set its individual flag, and, if the corresponding interrupt

enable bit is set, INT1 source of the 8051 core will be driven by a zero level. Software MUST

clear this register while serve the interrupt routine.

HPRchg= 1 → No action.

= 0 → Clears HSYNC presence change flag.

VPRchg= 1 → No action.

= 0 → Clears VSYNC presence change flag.

HPLchg= 1 → No action.

= 0 → Clears HSYNC polarity change flag.

VPLchg = 1 → No action.

= 0 → Clears VSYNC polarity change flag.

HFchg = 1 → No action.

= 0 → Clears HSYNC frequency change flag.

VFchg = 1 → No action.

= 0 → Clears VSYNC frequency change flag.

Vsync = 1 → No action.

= 0 → Clears VSYNC interrupt flag.

INTFLG (r) : Interrupt flag.

HPRchg= 1 → Indicates a HSYNC presence change.

VPRchg= 1 → Indicates a VSYNC presence change.

HPLchg= 1 → Indicates a HSYNC polarity change.

VPLchg = 1 → Indicates a VSYNC polarity change.

HFchg = 1 → Indicates a HSYNC frequency change or counter overflow.

VFchg = 1 → Indicates a VSYNC frequency change or counter overflow.

Vsync = 1 → Indicates a VSYNC interrupt.

INTEN (w) : Interrupt enable.

EHPR = 1 → Enables HSYNC presence change interrupt.

EVPR = 1 → Enables VSYNC presence change interrupt.

EHPL = 1 → Enables HSYNC polarity change interrupt.

EVPL = 1 → Enables VSYNC polarity change interrupt.

EHF = 1 → Enables HSYNC frequency change / counter overflow interrupt.

EVF = 1 → Enables VSYNC frequency change / counter overflow interrupt.

EVsync = 1 → Enables VSYNC interrupt.

7. DDC & IIC Interface

7.1 DDC2B Mode

To perform DDC2 function, S/W can configure the Slave A IIC block to act as EEPROM behavior. The slave

address of the Slave A block can be chosen by S/W as 5-bits, 6-bits or 7-bits. For example, if S/W chooses

5-bits slave address as 10100b, the slave IIC block A will respond to slave address 10100xxb and save the 2

Revision 1.0

- 12 -

2000/11/15

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