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MTV112EV-OTP View Datasheet(PDF) - Myson Century Inc

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MTV112EV-OTP Datasheet PDF : 19 Pages
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MYSON
TECHNOLOGY
MTV112E
(Rev 1.8)
5.3.2. To Read EEPROM
1. Write the slave address to MBUF (bit 0 = 1).
2. Set the S bit to Start.
3. After MTV112E transmits this byte, a MI interrupt will be triggered.
4. Set or reset the ACK flag according to the IIC protocol.
5. Read out the useless byte to MBUF to continue the data transfer.
6. After MTV112E receives a new byte, the MI interrupt is triggered again.
7. Reading MBUF also triggers the next receiving operation, but setting the P bit before reading can
terminate the operation.
* Please see the attachments about "Master IIC Timing Receiving".
5.4 Slave Mode IIC Function Block
The slave mode IIC block can be connected to HSDA/HSCL or ISDA/ISCL pins, and selected by the SLVsel
control bit. This block can receive/transmit data using the IIC protocol. S/W may set the SLVADR register to
determine which slave address the block should respond to.
In receiving mode, the block first detects an IIC slave address match condition then issues a SLVMI interrupt.
The data received from SDA is shifted into a shift register and written to the RCBUF latch. The first byte
loaded is the word address (slave address is dropped). This block also generates an RCBI (Receive Buffer
full Interrupt) each time the RCBUF is loaded. If S/W can't read out the RCBUF in time, the next byte will not
be written to RCBUF and the slave block will return NACK to the master. This feature guarantees the data
integrity of communication. A WADR flag can tell S/W if the data in RCBUF is a word address.
In transmission mode, the block first detects an IIC slave address match condition then issues a SLVMI. In
the meantime, the data pre-stored in the TXBUF is loaded into the shift register, results in TXBUF emptying
and generates a TXBI (Transmission Buffer Interrupt). S/W should write the TXBUF a new byte for the next
transfer before the shift register empties. Failure to do this will cause data corruption. The TXBI occurs each
time the shift register receives new data from TXBUF. The SLVMI is cleared by writing the SLVSTUS
register. The RCBI is cleared by reading the RCBUF. The TXBI is cleared by writing the TXBUF.
If the control bit ENSCL is set, the block will hold SCL low until the RCBI/TXBI is cleared.
*Please see the attachments about "Slave IIC Block Timing".
Reg name addr
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
MCTR 00h (w) LS1 LS0 LDFIFO M256 M128 ACK
P
S
MSTUS 00h (r) X SCLERR DDC2 BERR HFREQ FIFOH FIFOL BUSY
MBUF 10h (r/w) MBUF7 MBUF6 MBUF5 MBUF4 MBUF3 MBUF2 MBUF1 MBUF0
INTFLG 50h (r/w) HPRchg VPRchg HPLchg VPLchg HFchg VFchg FIFOI MI
INTEN 60h (w) EHPR EVPR EHPL EVPL EHF EVF EFIFO EMI
FIFO 70h (w) FIFO7 FIFO6 FIFO5 FIFO4 FIFO3 FIFO2 FIFO1 FIFO0
SLVCTR 90h (w) ENSLV SLVsel ERCBI ESLVMI ETXBI ENSCL X
X
SLVSTUS 91h (r) WADR SLVS RCBI SLVMI TXBI RWB ACKIN X
SLVSTUS 91h (w)
Write to clear SLVMI
RCBUF 92h (r) RCbuf7 RCbuf6 RCbuf5 RCbuf4 RCbuf3 RCbuf2 RCbuf1 RCbuf0
TXBUF 92h (w) TXbuf7 TXbuf6 TXbuf5 TXbuf4 TXbuf3 TXbuf2 TXbuf1 TXbuf0
SLVADR 93h (w) SLVadr7 SLVadr6 SLVadr5 SLVadr4 SLVadr3 SLVadr2 SLVadr1 X
MCTR (w) : Master IIC interface control register.
LS1, LS0
= 11 FIFOL is the status in which FIFO depth < 5.
= 10 FIFOL is the status in which FIFO depth < 4.
= 01 FIFOL is the status in which FIFO depth < 3.
= 00 FIFOL is the status in which FIFO depth < 2.
LDFIFO
= 1 FIFO will be written while S/W reads MBUF.
M256
= 1 Disables host writing EEPROM when address is over 256.
M128
= 1 Disables host writing EEPROM when address is over 128.
MTV112E Revision 1.8 05/18/2001
13/19
 

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