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Q32M210 View Datasheet(PDF) - ON Semiconductor

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Q32M210
Dual SPI
Two SPI interfaces are available supporting both master
and slave operation. Each synchronous 4wire interface
provides a clock, chip select, serial data in, and serial data
out connection. The SPI interface can be used to interface
with external devices such as nonvolatile memories,
displays, and wireless transceivers.
The SPI interfaces can be used either directly from the
ARM CortexM3 Processor or through the DMA Controller
SQI
The primary SPI interface can be configured to operate in
SQI (serial quad interface) mode. In SQI mode 4 bits are
interchanged simultaneously instead of 1 bit in SPI mode. In
this way, the throughput of the interface is increased by a
factor of 4 for the same clock frequency. The SQI interface
is typically used to access large, external NVM arrays.
I2C
The I2C interface supports both master and slave
operation. The interface operates at normal speed
(100 kbit/sec) and high speed (400 kbit/sec). Onchip
pullup resistors are available on the SDA and SCL pins.
The I2C interface can be used either directly from the
ARM CortexM3 Processor or through the DMA
Controller. The I2C slave address is programmable by the
application.
PCM
The pulsecode modulation (PCM) interface provides a
data connection between the device and external devices
such as Bluetooth or audio processors. The PCM interface
can operate both in master and slave mode. The master
device of a PCM transfer generates the frame signal.
The PCM interface can be used either directly from the
ARM CortexM3 Processor or through the DMA controller.
Two DMA channels are used with the PCM interface – one
for RX, and one for TX.
The PCM interface supports a wide variety of interface
protocols by reconfiguring the frame type and width, word
size and clock polarities. The PCM interface supports the
I2S data format directly for connecting to an I2S compatible
audio device. Audio data can be streamed to and from the
audio device over the PCM interface in I2S mode.
GPIO
GPIO pins can be configured as input or output signals.
The pins are powered from VDDIO0, VDDIO1, or VBATA
providing flexibility in the I/O voltage levels available.
Different I/O voltage levels may be supplied to VDDIO0
and VDDIO1 within the normal operating range. GPIO
functionality is shared with alternate functions on most
GPIO pins. The GPIO or alternate function is selected
through the application.
USB
The USB interface provides connectivity between the
ARM CortexM3 Processor and a USB host. The USB
interface operates as a USB Full Speed Device
(12 Mbit/sec). The USB physical interface (PHY) is
powered directly from VDDUSB. A minimum supply of
3 V is required. Typically VDDUSB will be powered from
the +5 V provided by the USB bus regulated down to 3.3 V.
The interface requires a 48 MHz clock which is provided
through the USB crystal oscillator. An external 48 MHz
crystal is required for this interface to operate. The USB
interface operates on a separate clock domain allowing the
rest of the system to continue to run on the slower internal
oscillator or external clock source. This enables reduced
power consumption, since the ARM CortexM3 Processor
can operate at a lower frequency than the USB clock when
USB is operational.
The USB interface interfaces to the ARM CortexM3
Processor through memorymapped control registers and
interrupts. The DMA may be used to transfer data between
the USB interface and the SRAM directly.
LCD
The device provides an onchip LCD driver capable of
driving up to 112 display segments of a 1/3 bias, 1/4 duty
cycle LCD display. The interface consists of four common
(COM) lines and twentyeight (28) segment (SEG) lines.
The drive voltages are sourced from VLCD and consist of
four voltages (0 V, 1/3 x VLCD, 2/3 x VLCD, and VLCD).
LCD Backlight
The LCD backlight driver provides an application
controlled current sink. It is programmable to sink
nominally between 0 mA to 10 mA. An LCD backlight may
be connected between VDBL and ILV. The current passing
through the LED is regulated based on the current setting set
by the application.
JTAG
The device contains a dedicated JTAG port for interfacing
to the ARM CortexM3 Processor and memories. The
device implements the standard JTAGDP protocol
provided by ARM, providing compatibility with many
external debugging systems.
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