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PSD835G2 View Datasheet(PDF) - STMicroelectronics

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PSD835G2 Datasheet PDF : 110 Pages
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PSD835G2
The
PSD835G2
Functional
Blocks
(cont.)
PSD8XX Family
Each of the two PLDs has unique characteristics suited for its applications They are
described in the following sections.
9.2.1 Decode PLD (DPLD)
The DPLD, shown in Figure 11, is used for decoding the address for internal and external
components. The DPLD can generate the following decode signals:
8 sector selects for the main Flash memory (three product terms each)
4 sector selects for the Flash Boot memory
(three product terms each)
1 internal SRAM select signal (three product terms)
1 internal CSIOP (PSD configuration register) select signal
1 JTAG select signal (enables JTAG-ISP on Port E)
2 internal peripheral select signals (peripheral I/O mode).
9.2.2 Complex PLD (CPLD)
The CPLD can be used to implement system logic functions, such as loadable counters
and shift registers, system mailboxes, handshaking protocols, state machines, and
random logic. The CPLD can also be used to generate 8 external chip selects, routed to
Port C or F. Although external chip selects can be produced by any Output MicroCell,
these eight external chip selects on Port C or F do not consume any Output MicroCells.
As shown in Figure 10, the CPLD has the following blocks:
24 Input MicroCells (IMCs)
16 Output MicroCells (OMCs)
Product Term Allocator
AND array capable of generating up to 196 product terms
Four I/O ports.
Each of the blocks are described in the subsections that follow.
The Input and Output MicroCells are connected to the PSD835G2 internal data bus and
can be directly accessed by the microcontroller. This enables the MCU software to load
data into the Output MicroCells or read data from both the Input and Output
MicroCells. This feature allows efficient implementation of system logic and eliminates
the need to connect the data bus to the AND logic array as required in most standard PLD
macrocell architectures.
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