PSD835G2 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
View to exact match
PSD835G2 Datasheet PDF : 110 Pages
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PSD835G2
7.0 PSD835G2
Register
Description and
Address Offset
PSD8XX Family
Table 6 shows the offset addresses to the PSD835G2 registers relative to the CSIOP base
address. The CSIOP space is the 256 bytes of address that is allocated by the user to the
internal PSD835G2 registers. Table 6 provides brief descriptions of the registers in CSIOP
space. For a more detailed description, refer to section 9.
Table 6. Register Address Offset
Register Name Port A Port B Port C Port D Port E Port F Port G Other*
Data In
00
01
10
11
30
40
41
Control
32
42
43
Data Out
04
05
14
15
34
44
45
Direction
06
07
16
17
36
46
47
Drive Select
08
09
18
19
38
48
49
Input Micro⇔Cell
0A
0B
1A
Enable Out
0C 0D 1C
4C
Output
Micro⇔Cells A
20
Output
Micro⇔Cells B
21
Mask
Micro⇔Cells A
22
Mask
Micro⇔Cells B
23
Flash Protection
C0
Flash Boot
Protection
C2
JTAG Enable
C7
PMMR0
B0
PMMR2
B4
Page
E0
VM
E2
Memory_ID0
F0
Memory_ID1
F1
Description
Reads Port pin as input,
MCU I/O input mode
Selects mode between
MCU I/O or Address Out
Stores data for output
to Port pins, MCU I/O
output mode
Configures Port pin as
input or output
Configures Port pins as
either CMOS or Open
Drain on some pins, while
selecting high slew rate
on other pins.
Reads Input Micro⇔Cells
Reads the status of the
output enable to the I/O
Port driver
Read – reads output of
Micro⇔Cells A
Write – loads Micro⇔cell
Flip-Flops
Read – reads output of
Micro⇔Cells B
Write – loads Micro⇔cell
Flip-Flops
Blocks writing to the
Output Micro⇔Cells A
Blocks writing to the
Output Micro⇔Cells B
Read only – Flash Sector
Protection
Read only – PSD Security
and Flash Boot Sector
Protection
Enables JTAG Port
Power Management
Register 0
Power Management
Register 2
Page Register
Places PSD memory
areas in Program and/or
Data space on an
individual basis.
Read only – Flash and
SRAM size
Read only – Boot type
and size
11
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