HEF4094BTS View Datasheet(PDF) - NXP Semiconductors.
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HEF4094BTS Datasheet PDF : 20 Pages
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NXP Semiconductors
HEF4094B
8-stage shift-and-store register
Table 7. Dynamic characteristics …continued
VSS = 0 V; Tamb = 25 C; for test circuit see Figure 11; unless otherwise specified.
Symbol Parameter
Conditions VDD
Extrapolation formula
tPLZ
LOW to OFF-state OE to QPn;
5V
propagation delay
see Figure 9 10 V
15 V
tsu
set-up time
D to CP;
5V
see Figure 10 10 V
15 V
th
hold time
D to CP;
5V
see Figure 10 10 V
15 V
tW
pulse width
minimum LOW 5 V
clock pulse;
see Figure 7
10 V
15 V
minimum HIGH 5 V
strobe pulse;
see Figure 8
10 V
15 V
fmax
maximum frequency see Figure 7 5 V
10 V
15 V
Min Typ Max Unit
-
80 160 ns
-
40 80 ns
-
30 60 ns
60 30 -
ns
20 10 -
ns
15 5
-
ns
+5 15 -
ns
20 5
-
ns
20 5
-
ns
60 30 -
ns
30 15 -
ns
24 12 -
ns
40 20 -
ns
30 15 -
ns
24 12 -
ns
5
10 -
MHz
11 22 -
MHz
14 28 -
MHz
[1] The typical values of the propagation delay and transition times are calculated from the extrapolation formulas shown (CL in pF).
Table 8. Dynamic power dissipation
VSS = 0 V; tr = tf 20 ns; Tamb = 25 C.
Symbol Parameter
VDD
Typical formula for PD (W)
PD
dynamic power 5 V
PD = 2100 fi + (fo CL) VDD2
dissipation
10 V
PD = 9700 fi + (fo CL) VDD2
15 V
PD = 26000 fi + (fo CL) VDD2
where:
fi = input frequency in MHz,
fo = output frequency in MHz,
CL = output load capacitance in pF,
VDD = supply voltage in V,
(fo CL) = sum of the outputs.
HEF4094B
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 11 — 29 August 2013
© NXP B.V. 2013. All rights reserved.
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