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HEF4094BP,652 View Datasheet(PDF) - NXP Semiconductors.

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Description
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HEF4094BP,652
NXP
NXP Semiconductors. NXP
HEF4094BP,652 Datasheet PDF : 20 Pages
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NXP Semiconductors
HEF4094B
8-stage shift-and-store register
a. Input waveform
VI
negative
pulse
0V
VI
positive
pulse
0V
90 %
10 %
VM
10 %
tf
tr
90 %
VM
tW
90 %
VM
10 %
tr
tf
90 %
VM
10 %
tW
001aaj781
VI
G
VDD
DUT
VEXT
VO
RL
RT
CL
001aaj915
b. Test circuit
Test data is given in Table 10.
Definitions for test circuit:
DUT = Device Under Test.
CL = load capacitance including jig and probe capacitance.
RL = load resistance.
RT = termination resistance should be equal to the output impedance Zo of the pulse generator.
Fig 11. Test circuit
Table 10. Test data
Supply voltage Input
VDD
5 V to 15 V
VI
VSS or VDD
tr, tf
20 ns
VEXT
tPHL, tPLH
open
tPHZ, tPZH
VSS
tPLZ, tPZL
VDD
Load
CL
50 pF
RL
1 k
HEF4094B
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 11 — 29 August 2013
© NXP B.V. 2013. All rights reserved.
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