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PM8611 View Datasheet(PDF) - PMC-Sierra

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PM8611 Datasheet PDF : 292 Pages
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SBSLITE™ Telecom Standard Product Data Sheet
Preliminary
7 Description
The PM8611 SBI336 Bus Serializer, SBSLITE, is a monolithic integrated circuit that implements
conversion between a byte-serial 77.76 MHz SBI336 bus and redundant 777.6 Mbit/s bit-serial
8B/10B-base SBI336S bus. In TelecomBus mode, the SBSLITE implements conversion between
a 77.76 MHz TelecomBus format and a redundant 777.6 Mbit/s bit-serial 8B/10B-base serial
TelecomBus format. In line with the bus conversion is a DS0 granular switch allowing any input
DS0 to be output on any output DS0.
The SBSLITE can be used to connect and switch high density T1/E1 framer devices supporting
an SBI bus with link layer devices supporting an SBI bus over a serial backplane. Putting a
Narrowband Switch Element (NSE) between the framer and link layer devices allows
construction of up to 20 Gbit/s NxDS0 switches.
In the ingress direction, the SBSLITE connects an incoming 77.76 MHz SBI336 stream to a pair
of redundant serial SBI336S LVDS links through a DS0 memory switch. In TelecomBus mode,
an incoming 77.76 MHz TelecomBus that has the J1 path fixed and all high order pointer
justifications converted to tributary pointer justifications can be switched through a VT granular
switch to a pair of redundant serial LVDS TelecomBus format links. The incoming data is
encoded into an extended set of 8B/10B characters and transferred onto two redundant 777.6
Mbit/s serial LVDS links. SBI or TelecomBus frame boundaries, pointer justification events and
master timing controls are marked by 8B/10B control characters. Incoming synchronized payload
envelopes (SPEs) may be optionally overwritten with the locally generated X23 + X18 + 1 PRBS
pattern for diagnosis of downstream equipment. The PRBS processor is configurable to handle
any combination of SPEs and can be inserted independently into either of the redundant LVDS
links. A DS0 memory switch provides arbitrary mapping of streams on the incoming SBI336 bus
stream to the working and protect LVDS links at DS0 granularity. In TelecomBus mode, a
VT1.5/VT2 memory switch provides arbitrary mapping of tributaries on the incoming
TelecomBus stream to the working and protect LVDS links. Multi-cast is supported.
In the egress direction, the SBSLITE connects two independent 777.6 Mbit/s serial LVDS links to
an outgoing SBI336 Bus. Each link contains a constituent SBI336S stream. Bytes on the links
are carried as 8B/10B characters. The SBSLITE decodes the characters into data and control
signals for a single 77.76 MHz SBI336 bus. Alternatively the SBSLITE decodes two independent
777.6 Mbit/s TelecomBus formatted serial LVDS links characters into a single 77.76 MHz
TelecomBus. A PRBS processor is provided to monitor the decoded payload for the X23 + X18 + 1
pattern in each SPE. The PRBS processor is configurable to handle any combination of
synchronized payload envelopes (SPEs) in the serial LVDS link. Data on the outgoing SBI336
bus stream may be sourced from either of the LVDS links.
An In-band signaling link over the serial LVDS links allows this device to be controlled by a
companion switching device, the Narrowband Switching Element, PM8620 NSE-20G. This link
can be used as communication link between a central processor and the local microprocessor.
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
17
Document ID: PMC-2010883, Issue 2
 

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