PM8315 View Datasheet(PDF) - PMC-Sierra

Part Name

Description

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PM8315

HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MULTIPLEXER

PMC-Sierra 

STANDARD PRODUCT

DATASHEET

PMC-1981125

ISSUE 7

PM8315 TEMUX

HIGH DENSITY T1/E1 FRAMER WITH

INTEGRATED VT/TU MAPPER AND M13 MUX

requests in the received DS2. AIS may be inserted in any of the low speed

tributaries in both multiplex and demultiplex directions.

When configured as a DS3 framer the unchannelized payload of the DS3 link is

available to an external device.

The SONET/SDH line side interface provides STS-1 SPE synchronous payload

envelope processing and generation, TUG3 tributary unit group processing and

generation within a VC4 virtual container and VC3 virtual container processing

and generation. The payload processor aligns and monitors the performance of

SONET virtual tributaries (VTs) or SDH tributary units (TUs). Maintenance

functions per tributary include detection of loss of pointer, AIS alarm, tributary

path signal label mismatch and tributary path signal label unstable alarms.

Optionally interrupts can be generated due to the assertion and removal of any

of the above alarms. Counts are accumulated for tributary path BIP-2 errors on a

block or bit basis and for FEBE indications. The synchronous payload envelope

generator generates all tributary pointers and calculates and inserts tributary

path BIP-2. The generator also inserts FEBE, RDI and enhanced RDI in the V5

byte. Software can force AIS insertion on a per tributary basis.

A SONET/SDH mapper maps and demaps up to 28 T1s, 21 E1s or a single DS3

into a STS-1 SPE, TUG3 or VC3 through an elastic store. The fixed stuff (R) bits

are all set to zeros or ones under microprocessor control. The bit asynchronous

demapper performs majority vote C-bit decoding to detect stuff requests for T1,

E1 and DS3 asynchronous mappings. The VT1.5/VT2/TU-11/TU-12 mapper

uses an elastic store and a jitter attenuator capability to minimize jitter

introduced via bit stuffing.

The TEMUX is configured, controlled and monitored via a generic 8-bit

microprocessor bus through which all internal registers are accessed. All

sources of interrupts can be masked and acknowledged through the

microprocessor interface.

PROPRIETARY AND CONFIDENTIAL

30

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