Part Name
Description
MFG CO.
ADC0804 Datasheet PDF : 16 Pages
D+1
D
D-1
56
34
12
+1 LSB
+1/2 LSB
0
-1/2 LSB
135
* QUANTIZATION ERROR
2
46
A-1 A A+1
-1 LSB
A-1 A A+1
TRANSFER FUNCTION
ERROR PLOT
FIGURE 11A. ACCURACY = ±0 LSB; PERFECT A/D
+1 LSB
D+1
D
D-1
5
6
3
4
1
2
A-1 A A+1
0
-1 LSB
1
3
6
* QUANTIZATION
ERROR
4
2
A-1 A A+1
TRANSFER FUNCTION
ERROR PLOT
FIGURE 11B. ACCURACY = ±1/2 LSB
FIGURE 11. CLARIFYING THE ERROR SPECS OF AN A/D CONVERTER
Understanding A/D Error Specs
A perfect A/D transfer characteristic (staircase wave-form) is
age and the particular points labeled are in steps of 1 LSB
(19.53mV with 2.5V tied to the VREF/2 pin). The digital output
codes which correspond to these inputs are shown as D-1, D,
and D+1. For the perfect A/D, not only will center-value (A - 1,
A, A + 1, . . .) analog inputs produce the correct output digital
codes, but also each riser (the transitions between adjacent
output codes) will be located ±1/2 LSB away from each center-
value. As shown, the risers are ideal and have no width. Correct
digital output codes will be provided for a range of analog input
voltages which extend ±1/2 LSB from the ideal center-values.
the same digital output code) is therefore 1 LSB wide.
The error curve of Figure 11B shows the worst case transfer
function for the ADC0802. Here the speciﬁcation guarantees
that if we apply an analog input equal to the LSB analog volt-
age center-value, the A/D will produce the correct digital code.
Next to each transfer function is shown the corresponding error
plot. Notice that the error includes the quantization uncertainty of
the A/D. For example, the error at point 1 of Figure 11A is
+1/2 LSB because the digital code appeared 1/2 LSB in advance
of the center-value of the tread. The error plots always have a
constant negative slope and the abrupt upside steps are always
1 LSB in magnitude, unless the device has missing codes.
Detailed Description
The functional diagram of the ADC0802 series of A/D
converters operates on the successive approximation princi-
ple (see Application Notes AN016 and AN020 for a more
detailed description of this principle). Analog switches are
closed sequentially by successive-approximation logic until
the analog differential input voltage [VlN(+) - VlN(-)] matches
a voltage derived from a tapped resistor string across the
reference voltage. The most signiﬁcant bit is tested ﬁrst and
after 8 comparisons (64 clock cycles), an 8-bit binary code
(1111 1111 = full scale) is transferred to an output latch.
The normal operation proceeds as follows. On the high-to-low
transition of the WR input, the internal SAR latches and the
shift-register stages are reset, and the INTR output will be set
high. As long as the CS input and WR input remain low, the
A/D will remain in a reset state. Conversion will start from 1 to
8 clock periods after at least one of these inputs makes a low-
to-high transition. After the requisite number of clock pulses to
complete the conversion, the INTR pin will make a high-to-low
transition. This can be used to interrupt a processor, or
otherwise signal the availability of a new conversion. A RD
operation (with CS low) will clear the INTR line high again.
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