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ADC0804 View Datasheet(PDF) - Intersil

Part NameDescriptionManufacturer
ADC0804 8-Bit, Microprocessor-Compatible, A/D Converters Intersil
Intersil Intersil
ADC0804 Datasheet PDF : 16 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
ADC0802, ADC0803, ADC0804
Electrical Specifications (Notes 1, 7) (Continued)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
Logic “1” Output Voltage, VOH lO = -360µA, V+ = 4.75V
2.4
-
-
V
Three-State Disabled Output
Leakage (All Data Buffers), ILO
VOUT = 0V
VOUT = 5V
-3
-
-
µA
-
-
3
µA
Output Short Circuit Current,
VOUT Short to Gnd TA = 25oC
4.5
6
ISOURCE
-
mA
Output Short Circuit Current,
VOUT Short to V+ TA = 25oC
9.0
16
-
mA
ISINK
NOTES:
1. All voltages are measured with respect to GND, unless otherwise specified. The separate AGND point should always be wired to the
DGND, being careful to avoid ground loops.
2. For VIN(-) VIN(+) the digital output code will be 0000 0000. Two on-chip diodes are tied to each analog input (see Block Diagram) which
will forward conduct for analog input voltages one diode drop below ground or one diode drop greater than the V+ supply. Be careful,
during testing at low V+ levels (4.5V), as high level analog inputs (5V) can cause this input diode to conduct - especially at elevated tem-
peratures, and cause errors for analog inputs near full scale. As long as the analog VIN does not exceed the supply voltage by more than
50mV, the output code will be correct. To achieve an absolute 0V to 5V input voltage range will therefore require a minimum supply volt-
age of 4.950V over temperature variations, initial tolerance and loading.
3. With V+ = 6V, the digital logic interfaces are no longer TTL compatible.
4. With an asynchronous start pulse, up to 8 clock periods may be required before the internal clock phases are proper to start the conversion
process.
5. The CS input is assumed to bracket the WR strobe input so that timing is dependent on the WR pulse width. An arbitrarily wide pulse
width will hold the converter in a reset mode and the start of conversion is initiated by the low to high transition of the WR pulse (see
Timing Diagrams).
6. CLK IN (pin 4) is the input of a Schmitt trigger circuit and is therefore specified separately.
7. None of these A/Ds requires a zero-adjust. However, if an all zero code is desired for an analog input other than 0V, or if a narrow full scale span
exists (for example: 0.5V to 4V full scale) the VIN(-) input can be adjusted to achieve this. See the Zero Error description in this data sheet.
Timing Waveforms
V+
RD
CS
DATA
OUTPUT
CL 10K
FIGURE 1A. t1H
2.4V
RD
0.8V
tr = 20ns
tr
90%
50%
10%
VOH
DATA
OUTPUTS
GND
t1H
90%
FIGURE 1B. t1H, CL = 10pF
V+
V+
10K
RD
DATA
CS
OUTPUT
CL
FIGURE 1C. t0H
2.4V
RD
0.8V
tr = 20ns
tr
90%
50%
10%
t0H
V+
DATA
OUTPUTS
VOI
10%
FIGURE 1D. t0H, CL = 10pF
FIGURE 1. THREE-STATE CIRCUITS AND WAVEFORMS
6-9
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