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ADC0804 View Datasheet(PDF) - Intersil

Part Name
Description
View to exact match
ADC0804 Datasheet PDF : 16 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
Functional Diagram
ADC0802, ADC0803, ADC0804
2
RD
1
CS 3
WR
READ
“1” = RESET SHIFT REGISTER
SET
Q “0” = BUSY AND RESET STATE
RESET
CLK R
19
CLK IN
4
CLK OSC
10
DGND
CLK A
CLK
GEN CLKS
G1 RESET
START F/F
V+ 20
(VREF)
9
VREF/2
LADDER
AND
DECODER
INPUT PROTECTION
FOR ALL LOGIC INPUTS
INPUT
TO INTERNAL
CIRCUITS
BV = 30V
CLK
D
DFF1
Q
CLK B
MSB
D
SUCCESSIVE
APPROX.
REGISTER
AND LATCH
8-BIT
SHIFT
REGISTER
R
RESET
START
CONVERSION
IF RESET = “0”
INTR F/F
AGND 8
6
VIN (+)
7
VIN (-)
DAC
VOUT
V+
+
-
LSB
Q
COMP
-
+
CLK A
D
DFF2
Q
THREE-STATE
OUTPUT LATCHES
XFER
G2
MSB
LSB
11 12 13 14 15 16 17 18
DIGITAL OUTPUTS
THREE-STATE CONTROL
“1” = OUTPUT ENABLE
SET
CONV. COMPL.
8 X 1/f
Q
5
INTR
6-6
 

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