ADC0802, ADC0803, ADC0804
Full Scale Adjust
(VREF) The full scale adjustment can be made by applying a
differential input voltage which is 11/2 LSB down from the
desired analog full scale voltage range and then adjusting
the magnitude of the VREF/2 input (pin 9) for a digital output
code which is just changing from 1111 1110 to 1111 1111.
When offsetting the zero and using a span-adjusted VREF/2
voltage, the full scale adjustment is made by inputting VMlN
to the VIN(-) input of the A/D and applying a voltage to the
VIN(+) input which is given by:
VIN(+)fSADJ = VMAX – 1.5 (---V----M-----A----X2----5-–--6--V-----M----I--N-----) ,
FIGURE 15. HANDLING ±5V ANALOG INPUT RANGE
Reference Accuracy Requirements
The converter can be operated in a pseudo-ratiometric
mode or an absolute mode. In ratiometric converter applica-
tions, the magnitude of the reference voltage is a factor in
both the output of the source transducer and the output of
the A/D converter and therefore cancels out in the ﬁnal digi-
tal output code. In absolute conversion applicatIons, both the
initial value and the temperature stability of the reference
voltage are important accuracy factors in the operation of the
A/D converter. For VREF/2 voltages of 2.5V nominal value,
initial errors of ±10mV will cause conversion errors of ±1
LSB due to the gain of 2 of the VREF/2 input. In reduced
span applications, the initial value and the stability of the
VREF/2 input voltage become even more important. For
example, if the span is reduced to 2.5V, the analog input LSB
voltage value is correspondingly reduced from 20mV (5V
span) to 10mV and 1 LSB at the VREF/2 input becomes
5mV. As can be seen, this reduces the allowed initial toler-
ance of the reference voltage and requires correspondingly
less absolute change with temperature variations. Note that
spans smaller than 2.5V place even tighter requirements on
the initial accuracy and stability of the reference source.
In general, the reference voltage will require an initial
adjustment. Errors due to an improper value of reference
voltage appear as full scale errors in the A/D transfer func-
tion. IC voltage regulators may be used for references if the
ambient temperature changes are not excessive.
The zero of the A/D does not require adjustment. If the
minimum analog input voltage value, VlN(MlN), is not ground, a
zero offset can be done. The converter can be made to output
0000 0000 digital code for this minimum input voltage by bias-
ing the A/D VIN(-) input at this VlN(MlN) value (see Applications
section). This utilizes the differential mode operation of the A/D.
The zero error of the A/D converter relates to the location of
the ﬁrst riser of the transfer function and can be measured by
grounding the VIN(-) input and applying a small magnitude
positive voltage to the VIN(+) input. Zero error is the difference
between the actual DC input voltage which is necessary to
just cause an output digital code transition from 0000 0000 to
0000 0001 and the ideal 1/2 LSB value (1/2 LSB = 9.8mV for
VREF/2 = 2.500V).
VMAX = the high end of the analog input range,
VMIN = the low end (the offset zero) of the analog range.
(Both are ground referenced.)
The clock for the A/D can be derived from an external source
such as the CPU clock or an external RC network can be
added to provIde self-clocking. The CLK IN (pin 4) makes
use of a Schmitt trigger as shown in Figure 16.
R ≅ 10kΩ
FIGURE 16. SELF-CLOCKING THE A/D
Heavy capacitive or DC loading of the CLK R pin should be
avoided as this will disturb normal converter operation.
Loads less than 50pF, such as driving up to 7 A/D converter
clock inputs from a single CLK R pin of 1 converter, are
allowed. For larger clock line loading, a CMOS or low power
TTL buffer or PNP input logic should be used to minimize the
loading on the CLK R pin (do not use a standard TTL buffer).
Restart During a Conversion
If the A/D is restarted (CS and WR go low and return high)
during a conversion, the converter is reset and a new con-
version is started. The output data latch is not updated if the
conversion in progress is not completed. The data from the
previous conversion remain in this latch.
In this application, the CS input is grounded and the WR
input is tied to the INTR output. This WR and INTR node
should be momentarily forced to logic low following a power-
up cycle to insure circuit operation. See Figure 17 for details.