PIC18CXX8
FIGURE 3-6: SLOW RISE TIME (MCLR TIED TO VDD)
5V
VDD
0V
1V
MCLR
INTERNAL POR
TPWRT
TDEADTIME
PWRT TIME-OUT
TOST
OST TIME-OUT
INTERNAL RESET
FIGURE 3-7: TIME-OUT SEQUENCE ON POR W/ PLL ENABLED (MCLR TIED TO VDD)
VDD
MCLR
IINTERNAL POR
PWRT TIME-OUT
OST TIME-OUT
TPWRT
TOST
TPLL
PLL TIME-OUT
INTERNAL RESET
TOST = 1024 clock cycles.
TPLL ≈ 2 ms max. First three stages of the PWRT timer.
2000 Microchip Technology Inc.
Advanced Information
DS30475A-page 33