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ADC08200 Просмотр технического описания (PDF) - Texas Instruments

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ADC08200 8-Bit, 20 Msps to 200 Msps, Low Power A/D Converter with Internal Sample and-Hold TI
Texas Instruments TI
ADC08200 Datasheet PDF : 27 Pages
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ADC08200
SNAS136M – APRIL 2001 – REVISED MARCH 2013
Specification Definitions
www.ti.com
APERTURE (SAMPLING) DELAY is that time required after the rise of the clock input for the sampling switch to
open. The Sample/Hold circuit effectively stops capturing the input signal and goes into the “hold” mode
tAD after the clock goes high.
APERTURE JITTER is the variation in aperture delay from sample to sample. Aperture jitter shows up as input
noise.
CLOCK DUTY CYCLE is the ratio of the time that the clock wave form is at a logic high to the total time of one
clock period.
DIFFERENTIAL NON-LINEARITY (DNL) is the measure of the maximum deviation from the ideal step size of 1
LSB. Measured at 200 Msps with a ramp input.
EFFECTIVE NUMBER OF BITS (ENOB, or EFFECTIVE BITS) is another method of specifying Signal-to-Noise
and Distortion Ratio, or SINAD. ENOB is defined as (SINAD – 1.76) / 6.02 and says that the converter is
equivalent to a perfect ADC of this (ENOB) number of bits.
FULL POWER BANDWIDTH is a measure of the frequency at which the reconstructed output fundamental
drops 3 dB below its low frequency value for a full scale input.
FULL-SCALE ERROR is a measure of how far the last code transition is from the ideal 1½ LSB below VRT and is
defined as:
Vmax + 1.5 LSB – VRT
where
• Vmax is the voltage at which the transition to the maximum (full scale) code occurs
(1)
INTEGRAL NON-LINEARITY (INL) is a measure of the deviation of each individual code from a line drawn from
zero scale (½ LSB below the first code transition) through positive full scale (½ LSB above the last code
transition). The deviation of any given code from this straight line is measured from the center of that code
value. The end point test method is used. Measured at 200 Msps with a ramp input.
INTERMODULATION DISTORTION (IMD) is the creation of additional spectral components as a result of two
sinusoidal frequencies being applied to the ADC input at the same time. it is defined as the ratio of the
power in the second and third order intermodulation products to the power in one of the original
frequencies. IMD is usually expressed in dBFS.
MISSING CODES are those output codes that are skipped and will never appear at the ADC outputs. These
codes cannot be reached with any input value.
OUTPUT DELAY is the time delay after the rising edge of the input clock before the data update is present at
the output pins.
OUTPUT HOLD TIME is the length of time that the output data is valid after the rise of the input clock.
PIPELINE DELAY (LATENCY) is the number of clock cycles between initiation of conversion and when that
data is presented to the output driver stage. New data is available at every clock cycle, but the data lags
the conversion by the Pipeline Delay plus the Output Delay.
POWER SUPPLY REJECTION RATIO (PSRR) is a measure of how well the ADC rejects a change in the power
supply voltage. For the ADC08200, PSRR1 is the ratio of the change in Full-Scale Error that results from a
change in the DC power supply voltage, expressed in dB. PSRR2 is a measure of how well an AC signal
riding upon the power supply is rejected from the output and is here defined as
where
• SNR0 is the SNR measured with no noise or signal on the supply line
• SNR1 is the SNR measured with a 1 MHz, 200 mVP-P signal riding upon the supply lines
(2)
SIGNAL TO NOISE RATIO (SNR) is the ratio, expressed in dB, of the rms value of the input signal at the output
to the rms value of the sum of all other spectral components below one-half the sampling frequency, not
including harmonics or d.c.
8
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