SNAS136M – APRIL 2001 – REVISED MARCH 2013
While a single voltage source is recommended for the VA and VDR supplies of the ADC08200, these supply pins
should be well isolated from each other to prevent any digital noise from being coupled into the analog portions
of the ADC. A choke or 27Ω resistor is recommended between these supply lines with adequate bypass
capacitors close to the supply pins.
As is the case with all high speed converters, the ADC08200 should be assumed to have little power supply
rejection. None of the supplies for the converter should be the supply that is used for other digital circuitry in any
system with a lot of digital power being consumed. The ADC supplies should be the same supply used for other
No pin should ever have a voltage on it that is in excess of the supply voltage or below ground by more than 300
mV, not even on a transient basis. This can be a problem upon application of power and power shut-down. Be
sure that the supplies to circuits driving any of the input pins, analog or digital, do not come up any faster than
does the voltage at the ADC08200 power pins.
THE DIGITAL INPUT PINS
The ADC08200 has two digital input pins: The PD pin and the Clock pin.
The PD Pin
The Power Down (PD) pin, when high, puts the ADC08200 into a low power mode where power consumption is
reduced to about 1.4 mW with the clock running, or to about 1 mW with the clock held low. Output data is valid
and accurate about 1 microsecond after the PD pin is brought low.
The digital output pins retain the last conversion output code when either the clock is stopped or the PD pin is
The ADC08200 Clock
Although the ADC08200 is tested and its performance is ensured with a 200 MHz clock, it typically will function
well with clock frequencies from 10 MHz to 230 MHz.
The low and high times of the clock signal can affect the performance of any A/D Converter. Because achieving
a precise duty cycle is difficult, the ADC08200 is designed to maintain performance over a range of duty cycles.
While it is specified and performance is ensured with a 50% clock duty cycle and 200 Msps, ADC08200
performance is typically maintained with clock high and low times of 0.65 ns and 0.87 ns, respectively,
corresponding to a clock duty cycle range of 13% to 82.5% with a 200 MHz clock. Note that minimum low and
high times may not be simultaneously asserted.
The CLOCK line should be series terminated at the clock source in the characteristic impedance of that line if the
clock line is longer than
• tr is the clock rise time
• tprop is the propagation rate of the signal along the trace
Typical tprop is about 150 ps/inch (59 ps/cm) on FR-4 board material.
If the clock source is used to drive more than just the ADC08200, the CLOCK pin should be a.c. terminated with
a series RC to ground such that the resistor value is equal to the characteristic impedance of the clock line and
the capacitor value is
• tPD is the signal propagation rate down the clock line
• "L" is the line length
• ZO is the characteristic impedance of the clock line
Submit Documentation Feedback
Product Folder Links: ADC08200
Copyright © 2001–2013, Texas Instruments Incorporated